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  • Stretching data during 2 clock cycle
    Hi All, I have a question about clocking. I want to achieve "result 2".(see attachment) However i am having problem getting the correct system verilog to work. I have no idea why it did not as expected. I keep on getting result 1 :( Need some advice here.Thanks. Each character is 5ns wide. clkA 10101010 clkb ...
    Posted to Functional Verification (Forum) by gilazilla on Thu, Sep 22 2011
Page 1 of 1 (1 items)