Home > Community > Search
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Community Search 

Page 1 of 1 (2 items)
  • Pin mismatch between schematic and symbol in Virtuoso
    Hi, I have a symbol view which has bus notation for pins like A<1:10>, B<1:10> (imported from verilog). But the corresponding schematic has single bit notation, like A<0>, A<1> etc...(imported from a spice netlist) I want to modify the schematic, by creating the bus style notation and remove the single pins. Is there an ...
    Posted to Custom IC Design (Forum) by asta51 on Fri, Feb 1 2013
  • Number of fingers differ between schematic and layout
    I am using IC 6.1.5 and I have views of standard cells (schematic and layout) which are not passing LVS (Calibre). The issue is that in layout I have MOS with a certain number of fingers whereas the schematic have just one finger with the total width.  Example:  Layout:       M0 w=0.42u ...
    Posted to Custom IC Design (Forum) by asta51 on Fri, Nov 23 2012
Page 1 of 1 (2 items)