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 Community Search 

Page 1 of 1 (4 items)
  • short violations
     HI All, In My Design I got short violations on signal nets only .In my case one net create huge violations and another case some drc violations are there . I did this way to rectify drc violations---> dbGet Selected.net.name---> dbdeleteObj--> setNanoRoutemode -quiet withecoroute true  setNanoRoutemode -quiet TimingDriven ...
    Posted to Digital Implementation (Forum) by pandamaneni on Sun, Apr 7 2013
  • IR DROP (vstrom)
     Hi All, I did IR drop in vstrom cadence.I have results along with me. dynamic ir drop 7% (vcc) but i want  see my result in encounter .i tried with these following steps Power> Report>power & rail result>  Browse> ../fppg/vstorm/result_dynamic_VCC/ "loadstate" but encounter shows error ...i.e.., there ...
    Posted to Digital Implementation (Forum) by pandamaneni on Tue, Feb 26 2013
  • How dump lvs netlist from encounter ?
     Hi Guys, After merging the gds in encounter I dumped netlist only I tried below commands saveNetlist filename_v2lvs.v.gz saveNetlist -includePGporInformation filename_lvs.v.gz Right Now I am using encounter 11.11v whenever I ran calibrelvs ports/nets are mismatched in layout.spi ,instances are passed  How to debug those ...
    Posted to Digital Implementation (Forum) by pandamaneni on Thu, Jan 31 2013
  • How to fix via power spacing violations in encounter
    Hi Guys, Could You Please tell me how to fix via power spacing violations in encounter? Is there Any chances this via power spacing violations, it will create short violations ? When I running Claibrelvs  some power nets like VDD VCC ports are mismatched
    Posted to Digital Implementation (Forum) by pandamaneni on Thu, Jan 31 2013
Page 1 of 1 (4 items)