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 Community Search 

Page 1 of 2 (12 items) 1 | 2 | Next >
  • RTL Compiler: Unavoid the tiecells from library
    Hi, after I synthesized the VHDL-code using RTL Compiler 9.10, I want to insert TIE1 and TIE0 cells, but I got this error: ################## rc:/> insert_tiehilo_cells -hi TIE1 -lo TIE0 top_cell_name Error   : Specify a tiecell which is not avoided. [UTUI-215] [insert_tiehilo_cells]         : ...
    Posted to Logic Design (Forum) by haikom on Thu, Feb 3 2011
  • Re: spectre simulation error
     hi, are all jobs submitted to machines using the same operation system? If it is a mixed setup, try to submit the jobs only to machines using the same operating system (os) to find out, whether it is a problem of the os-setup/installation. regards haikom
    Posted to Custom IC Design (Forum) by haikom on Mon, Aug 24 2009
  • Re: VerilogA Problem in MMSIM-7.1
    Hi, another idea: have a look at your environment variable PATH and enshure, that the path to gcc points to the correct directory in the correct MMSIM installation tree. Maybe this causes trouble.  Good luck haikom
    Posted to Custom IC Design (Forum) by haikom on Thu, Jun 11 2009
  • Re: VerilogA Problem in MMSIM-7.1
    Hi,  after the installation of MMSIM 7.1, did you configured all packages? During this process veriloga and vhdlams libraries will be compiled and some links will be defined. Maybe this causes problem?  Kind regards haikom
    Posted to Custom IC Design (Forum) by haikom on Mon, Jun 8 2009
  • Re: Configuring Cadence
     Hi, you just have to create the softlink "tools" inside the install directory (ln -s tools.lnx86 tools), define the location of the license file (setenv CDS_LIC_FILE port@licserver for network licenses in c-shells) and add the path "installDir/tools/bin" to the path variable (set path = (installDir/tools/bin ...
    Posted to Custom IC Design (Forum) by haikom on Mon, Jun 8 2009
  • Re: IUS 6.11 USR3 - worklib is not updated after compiling
    Hi all, the problem seems to be solved. I looked at the environment variables an saw, that there were two entries: "$IUSDIR/tools/nclaunch/bin/64bit" AND "$IUSDIR/tools/bin" After I removed the first entry, the problem with the non-updated worklib was solved. The I looked into the install.pdf and there is written, that only ...
    Posted to Functional Verification (Forum) by haikom on Thu, Jun 4 2009
  • Re: Cadence IC 6.1.3 Simualtion
     Hi, do you mean the libXt.so... error? Search for this lib inside the cadence installation tree. If you find this file, add the path to the environment variable LD_LIBRARY_PATH. Please take care whether you are on a 32- or 64-bit machine and choose the correct directory.  Regards haiko
    Posted to Custom IC Design (Forum) by haikom on Wed, Jun 3 2009
  • Re: SOC Encounter, please help
    Hi, you just want to have a test-point (pad without any logic or esd protection)? If there is no test pad in your i/o library, I would place it as a macro. Therefore you have to describe the pad as lef file and specify these instance as don't touch during synthesis.  Regards haiko
    Posted to Digital Implementation (Forum) by haikom on Wed, Jun 3 2009
  • IUS 6.11 USR3 - worklib is not updated after compiling
    Hi, I installed the nclaunch version 6.11 at a linux machine (RedHat 4 Enterprise Ed.). After this I configured the product so that all vhdl std. libraries where compiled. When I try to compile vhdl or verilog code, there is no change in the worklib (no '+' at the left side of the worklib)!!! The older version (IUS 5.7) worked whithout ...
    Posted to Functional Verification (Forum) by haikom on Wed, Jun 3 2009
  • Re: How to plot device parameters from transient sims.
    Hi Eric, I'm did not understand completely, what you want. The save statement "save M1:oppoint ..." seams to save the final operating point parameters. If you want to access theses values you can do this using the following way: \i results \o  (tranOp subckts instance "tranViolations-violations" model ...
    Posted to Custom IC Design (Forum) by haikom on Mon, Oct 27 2008
Page 1 of 2 (12 items) 1 | 2 | Next >