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Page 1 of 1 (4 items)
  • Re: error in output waveform
     thank you so much sir for your time and i appreciate your suggestion and will surely work upon it. i will surely contact you again in future if i feel that m not able to find a solution to my problem.
    Posted to Functional Verification Shared Code (Forum) by lov sareen on Sun, Jul 3 2011
  • error in output waveform
     hi, i am doing a project on synchronous fifo design using verilog. below written is my coding. after simulation the waveform is showing error regarding its not giving value of rdata_valid and is showing a red line in waveform and due to it address is also not being taken.i have attached the waveform also. the logic for write logic ...
    Posted to Functional Verification Shared Code (Forum) by lov sareen on Thu, Jun 30 2011
  • error in waveform generation
     hi, i am doing a project on synchronous fifo design using verilog. below written is my coding. after simulation the waveform is showing error regarding its not giving value of rdata_valid and is showing a red line in waveform and due to it address is also not being taken.i have attached the waveform also. the logic for write logic is also ...
    Posted to Logic Design (Forum) by lov sareen on Thu, Jun 30 2011
  • not able to write logic
    hi, i am making a project on synchronous FIFO block using verilog HDL. i have made a top level module which includes read control logic, write control logic, memory array(includes just inputs and outputs). now to read the 16 bit input values i have made a module for read control logic so Can u plz tell me the logic to generate almost empty flag ...
    Posted to Logic Design (Forum) by lov sareen on Thu, Jun 23 2011
Page 1 of 1 (4 items)