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 Community Search 

Page 1 of 2 (15 items) 1 | 2 | Next >
  • Re: Simulator Inaccuracy?
    It seems that odd behaviour was due to my setup referncing the wrong pdk files. The files were updated my machine was still pointing to the old parameters causing the odd behaviour. So a restart now and then does really help :)
    Posted to Custom IC Design (Forum) by MTP3 on Fri, Feb 21 2014
  • Simulator Inaccuracy?
    Hi! I am facing a very interesting issue that I have not seen/experienced before in cadence. I have a delay line and I am interested in finding the delay through it. When I use a vpulse to generate the input signal I get the expected output clock after the expected delay with no unusual effects. But when I generate the input clock using a verilog ...
    Posted to Custom IC Design (Forum) by MTP3 on Fri, Feb 21 2014
  • Re: Phase noise of frequency multiplier
    Many thanks for the reply Shawn. So here goes. 1)I have verified that the ROs are all oscillating at the same frequency (although there is some variation in their oscillation frequency due to device noise etc) but generally all of them oscillate in the same frequency range with a relatively small offset. 2) As recommended in the spectre RF manuals ...
    Posted to RF Design (Forum) by MTP3 on Tue, Nov 19 2013
  • Phase noise of frequency multiplier
    Hi! I am trying to simulate a frequency multiplier. The oscillators are simple ring oscillators oscillating at 2GHz made form inverters.What the multiplier circuit is that it cancels the fundamental tone and retains/preservs the 3rd harmonic(3,6,9...) and cancels the other harmoics like 1,2,4,5.......   The problem; I am interested in ...
    Posted to RF Design (Forum) by MTP3 on Mon, Nov 18 2013
  • Re: LC Oscillators startup
    Hi again! Many thanks for the advice tkhan and Tawna. So some updates about the circuits. I have manged to startup the oscillator with some redesigning of the circuit (I basically had to increase the negative resistance contribution of the feedback transistors). I think the issue(probably) was that the loses in the varactors were not negligible. ...
    Posted to RF Design (Forum) by MTP3 on Sun, Jun 10 2012
  • Re: LC Oscillators startup
    Hi!  Many thanks for the replies tkhan and Tawna. Thanks for the documents I will go through them and will update about the progress.  
    Posted to RF Design (Forum) by MTP3 on Wed, Jun 6 2012
  • Re: LC Oscillators startup
    Many thanks for the reply Tawna. I am trying the a transient analysis just to see if the oscillator starts up or not. Please correct me if I am wrong but doing a PSS also requires some kind of transient run, is it so?.  
    Posted to RF Design (Forum) by MTP3 on Tue, Jun 5 2012
  • Re: LC Oscillators startup
    Hi!  Many thanks for the reply tkhan  I think I have it right at least theoratically the values are satisfied as mentioned in Ali Hajmiri's paper that the negative resisitance contribution from the active devices(PMOS+NMOS) should be 3 times the inductor losses gL( for a Q of 13 this comes out to be 2.9mS @ 2.1GHz) and I have a ...
    Posted to RF Design (Forum) by MTP3 on Mon, Jun 4 2012
  • LC Oscillators startup
    Hi all! I a trying to simulate a cross coupled LC oscíllator using the components from the pdk provider (ST microelectronics) in my case. Ths issue I am facing is kind of confusing me that is the oscillator does not start oscillating if I attach a series resistor with the caps(the resistor is to model the loses in the caps, which ...
    Posted to RF Design (Forum) by MTP3 on Sun, Jun 3 2012
  • Timing checks in ncsim
    HI! I am new to using ncsim and all so please excuse for simplistic questions, so anyways I want to simulate a state machine made up of DFFs (with no reset) and some logic gates. When I try to simluate the design electronically everything works fine but if use verilog descriptions of standard library cells (provided by the vendor) I get these X ...
    Posted to Functional Verification (Forum) by MTP3 on Wed, May 16 2012
Page 1 of 2 (15 items) 1 | 2 | Next >