Home > Community > Search
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Community Search 

Page 1 of 5 (42 items) 1 | 2 | 3 | 4 | 5 | Next >
  • Re: clock gating in RC
     That looks right.  If you want to limit the fanout of the clock_gater to 16, then you will also want to add the lp_clock_gating_max_flops attribute, and set it to 16.  However, I think it is better to let the PnR tool clone the clock gaters, if necessary, to meet timing to the enable signal. Also, be sure you set the ...
    Posted to Logic Design (Forum) by bmiller on Thu, Apr 10 2014
  • Re: LEC - Conformal RTL to netlist mismatch
     Sure.  Sequential merging is when the synthesis tool merges two or more flops into one because they have the exact same function.  Sequential constant is when the synthesis tool optimizes away flops that are always tied to 1'b1 or 1'b0.  
    Posted to Logic Design (Forum) by bmiller on Wed, Apr 2 2014
  • Re: How to get best results from synthesis
    Kirtesh,  What you are asking for is not simple.  Power domains and multiple modes make for a complex synthesis environment.  But, the write_template command in RC will give you an excellent starting point.  I think the write_template options you need are -power and -cpf (for power domains).    rc:/>  ...
    Posted to Digital Implementation (Forum) by bmiller on Tue, Oct 8 2013
  • Re: What does Constant hierarchical Pin(s) means in RTL compiler?
     Constant hierarchical pins are generally not a problem, but they are still worth investigating.  When RC propagates constants across hierarchical boundaries, it will tie the pin to 1'b0.  The other side of that hierarchical pin will have nothing attached to it.  It effectively becomes an unused hierarchical pin, but RC, by ...
    Posted to Logic Design (Forum) by bmiller on Wed, Sep 11 2013
  • Re: Include a IP netlist during Synthesis of a complete design
    You would read your HDL and elaborate as follows:   read_hdl -v2001|-sv <rtl_files>   read_hdl -netlist <ip_netlsit>   Then, you would preserve the IP block:   set_attr preserve true [find / -subdesign <ip_module_name>]   Continue with synthesis as you normally would.  The IP module will not ...
    Posted to Logic Design (Forum) by bmiller on Fri, Aug 16 2013
  • Re: RTL compiler to minimize area
    glennramalho,  RTL-Compiler does not accept a max_area constraint because the tool's philosophy is to always synthesize to the minimum area necessary to meet your other goals (timing and power).  Lower area is pointless if you cannot meet timing.  And, why would anyone want more area than necessary?  With those thoughts ...
    Posted to Logic Design (Forum) by bmiller on Wed, Jun 19 2013
  • Re: using ModelSim/QuestaSim VCD file in RTL compiler
     It is great that you got it to work with vcd2saif.  However, that should not be necessary.  I suspect you need to use the -vcd_scope (or -vcd_module in older releases) option to read_vcd in order to select the "scope" in the VCD that you want to apply to the top design in RC.  It is very common for a VCD to only ...
    Posted to Logic Design (Forum) by bmiller on Tue, Jun 18 2013
  • Re: cell_leakage_power
     RTL-Compiler uses the state-dependent leakage power tables provided in the .lib if they exist.     
    Posted to Logic Design (Forum) by bmiller on Tue, May 21 2013
  • Re: Exclude Paramter name/value during module generation in LEC
     View solution "20092848" on support.cadence.com for information on how to handle this.  To summarize, this is what you need to do:  However if the default naming convention for module names is changed during synthesis with DC/RC, then the above commands would not match module names in LEC. To resolve this, you need ...
    Posted to Logic Design (Forum) by bmiller on Fri, May 10 2013
  • Re: Problem occurs when reading vcd in RTL Compiler
    I don't think it makes sense to synthesize the testbench.  In fact, I am surprised tb.v is synthesizable at all.  tb.v does not represent hardware (I assume), so I would expect it to contain verilog constructs that cannot be synthesized.  The VCD file can contain data for both the testbench, and the design.  You just need ...
    Posted to Logic Design (Forum) by bmiller on Wed, Mar 27 2013
Page 1 of 5 (42 items) 1 | 2 | 3 | 4 | 5 | Next >