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  • Importing a VHDL file into Virtuoso for mixed signal sim
    Hello, I am experiencing quite a few problems when trying to include a VHDL file into a mixed signal testbench to verify its functionalities. The testbench is created (config + schematic), the vhdl file was imported with  "VHDL Import" (following Cadence Help Docs...). The tool creates 3 cell views: entity, rtl and symbol. After ...
    Posted to Custom IC Design (Forum) by FernandoLeite on Thu, May 3 2012
Page 1 of 1 (1 items)