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Page 1 of 8 (79 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »
  • Re: VCD and irun
    you can generate a vcd either from tcl commands or via system tasks.  take a look at the following pdf for more information...  <IES_install_location>/doc/Debugging/Debugging.pdf   In the pdf take a look at the section titled "Generating a Value Change Dump (VCD) File"   Hope that helps. Mickey
    Posted to Logic Design (Forum) by John "Mickey" Rodriguez on Fri, May 18 2012
  • Re: How do I get nc-sim to recongnize a .sv file?
    Hi Jackie,  Sounds like you are using either "ncverilog" or "ncvlog" to do the compile. If you are using "ncvlog" you should add -sv to your command line to invoke the systemverilog parser. if you are using "ncverilog" command, you can simpy replace the "ncverilog" command with ...
    Posted to Functional Verification (Forum) by John "Mickey" Rodriguez on Thu, Aug 25 2011
  • Re: Failed to find SETUP/HOLD timingcheck
    Hello, The message is indicating that you have HOLD and SETUP timing checks in the sdf file, but there is no SETUP or HOLD timing checks specified in the verilog specify block of the RTL.  Consequently the simulator is not able to annotate those timing checks.  This will not cause the simulator to exit or fail, but it will result in the ...
    Posted to Functional Verification (Forum) by John "Mickey" Rodriguez on Tue, Jul 26 2011
  • Re: Forcing a VHDL signal from a Verilog Test/Env
    Hi Ashfaq, You need to use $nc_force to force a vhdl down in the design hierarchy from a verilog testbench.  It's fairly simple.    $nc_force ("source", "value", "after_time", "rel_time", "repeat_time",  "cancel_time", "verbose"); for example, ...
    Posted to Functional Verification (Forum) by John "Mickey" Rodriguez on Fri, Jul 22 2011
  • Re: RE: UPF to CPF conversion
    Sorry Betty I misunderstood your questions.  to read in a UPF and convert it to a CPF you will need to read it in and write out the corresponding *.cpf by adding instructions to do so in the *.do file that you pass to CLP.  The script would be something like the following:  CLP.do script --------------------- set lowpower option ...
    Posted to Logic Design (Forum) by John "Mickey" Rodriguez on Wed, Jun 1 2011
  • Re: UPF to CPF conversion
    Hi Betty, PIA is now integrated directly into the CLP user interface. When in the CLP gui (lec -lp –verify –gui) in the upper left pane, expand the Design Setup section and click on Power Spec. This is where you can enter the appropriate power intent content. Best regards, Mickey
    Posted to Logic Design (Forum) by John "Mickey" Rodriguez on Mon, May 30 2011
  • Re: Memory Content Viewer in Simvision
    Hi Paul,  I just realized that I didn't answer your second question about memory preload.  You can preload memories using a tcl command.  For more information take a look at the memory command in the tcl command reference within the IES installation (<ies_install>/tools/doc/tclcmdref/tclcmdref.pdf).  Best ...
    Posted to Functional Verification (Forum) by John "Mickey" Rodriguez on Wed, Mar 30 2011
  • Re: Memory Content Viewer in Simvision
    Hi Paul, To dump the content of memories in the waveform database... if you are using tcl probe commands, add -memories to the probe command, eg.  probe some.hierarchical.path. -all -memories -depth all the above command will problem all signals within the some.hiearchical.path instance and below, including memories. If you re ...
    Posted to Functional Verification (Forum) by John "Mickey" Rodriguez on Wed, Mar 30 2011
  • Re: Elaboration error in irun. IUS
    Try using -partialdesign. this will allow elab to complete even if some instances are not defined. However be aware that some errors cannot be found until others are fixed. For example lets say that an instance is not bound. That problem will lead to an elab error. If there are other errors under the hierarchy of the bound instance, they ...
    Posted to Functional Verification (Forum) by John "Mickey" Rodriguez on Tue, Mar 29 2011
  • Re: UPF to CPF conversion
    Hi. PIA is now integrated directly into the CLP user interface. When in the CLP gui (lec -lp –verify –gui) in the upper left pane, expand the Design Setup section and click on Power Spec. This is where you can enter the appropriate power intent content. Best regards, Mickey
    Posted to Logic Design (Forum) by John "Mickey" Rodriguez on Tue, Mar 22 2011
Page 1 of 8 (79 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »