Re: RE: Forcing a VHDL signal from a Verilog Test/Env
Hi,
I was able to source to the signal of interest, but i have a requirement to keep giving different values to that signal of interest.
I tried something like this, which din't work out.
repeat(4) begin
$nc_force("source", "reg") ;
reg = reg+1'b1;
end
The reg value in my simulation keeps incrementing but the ...