Home > Community > Search
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Community Search 

Page 1 of 1 (2 items)
  • Clock Tree Synthesis of a delay chain (tapped delay line)
    In RTL, clock buffers and MUXes are used to create a delay chain/tapped delay line. These are preserved in synthesis and hence they appear in the netlist. If this netlist is used, during Clock Tree Synthesis (CTS) stage, the tool (SoC Encounter) hangs and does not move forward saying that the clocks are already built and cannot be removed. If ...
    Posted to Digital Implementation (Forum) by randomax on Sun, Jul 6 2014
  • Propagate a clock from .LIB of a block
    Hello all,    I am trying to synthesize a module which has a .LIB for one of the blocks. The block has internal clock generators and requires to create a clock on one of the block's ports. I can create the clocks in the top-level by providing hierarchical path. However, I am not able to see the generated clocks come out of the ...
    Posted to Logic Design (Forum) by randomax on Mon, Apr 30 2012
Page 1 of 1 (2 items)