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  • Cadence Encounter doesn't fix hold violations?
    Hi everyone,please help me with the next problem: I'm designing a digital IC based on FPGA-verified source code using Cadence tools: Encounter for P&R and optimization and Incisive simulator (NCSim may be the second name) for checking the resulting waveforms.After P&R, in post-route stage, I optimized design using the next commands: optDesign ...
    Posted to Digital Implementation (Forum) by Kuxx on Tue, Nov 13 2012
Page 1 of 1 (1 items)