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Page 1 of 4 (35 items) 1 | 2 | 3 | 4 | Next >

Problem in LVS checkingin Layout
Hi, In my layout DRC checking is fine. But in layout ,when I am trying LVS checking, I am getting errors like below in attached . I am using Cadence Virtuoso . Assura (tm) ...

Posted to RF Design (Forum) by Analog Design on Wed, Jul 13 2011
Help in stability analysis of LNA....
Hi, In stern's stability analysis, I am getting both Kf and Bf1 parameter greater than one. Then what is stability level in my LNA design . What is fault in design and why this occures? I am using Cadence spectre(IC561) for rf analysis. Can anyone help me?

Posted to RF Design (Forum) by Analog Design on Tue, Jun 14 2011
Re: Help for sensitivity analysis of LNA.?
Hi Tawna, Whatever you have gaussed , that's right. Actully I wan to do ac sens analysis in cadence spectre. But I do not know proper procedure to do it. Can you give me detail procedure to do sens analysis in Cadence spectre? I am using (IC561) simulator.

Posted to RF Design (Forum) by Analog Design on Tue, Jun 14 2011
Help for sensitivity analysis of LNA.?
Hi, I wan to do sensitivity analysis of LNA in cadence spectre(IC 561). I have already done S-parameter analysis in Cadence Spectre(IC561). Can anyone help me in sensitivity analysis?

Posted to RF Design (Forum) by Analog Design on Sun, Jun 12 2011
Help for capacitor layout in cadence spectre
Hi, In my schematic +ve terminal of capacitor is connected to one terminal and -ve terminal is connected to some fixed DC voltage. I am donig layout in cadence vurtuso version IC514 . It is giving some error like below The minimum overlap of M1 ground plate to LSM is 10um . What does it mean ? Can I ...

Posted to RF Design (Forum) by Analog Design on Wed, Jun 1 2011
Is it possible to check signal at a node inside chip after fibrication?
Hi ....., I wan to check signal strength at a particular node which is connected between two modules inside chip(after fibrication) . Is it possible to check it? ...........,If possible then how to do it ?

Posted to Custom IC Design (Forum) by Analog Design on Mon, May 16 2011
Help for pnoise simulation in cadencespectre for VCO simulation
Hi, When I am doing pnosie analysis in cadence spectre (IC 416) , the simulation prematuarly teminated & error flushing like below Provided I have fixed tstb =200ns for beat frequency = 10MHz ///////////////////////////////////////////////////////////////////////////////////////////////// pss has reached the maximum ...

Posted to RF Design (Forum) by Analog Design on Mon, May 16 2011
Help for checking gain of VCO in cadence spectre
Hi, I am facing difficulty in checking VCO gain(frequency vs inputvoltage) and linearity (frequency vs inputvoltage) and lock range . Can anyone help me how to do checking of above simulation result in cadence spectre(IC.4....).

Posted to RF Design (Forum) by Analog Design on Tue, May 10 2011
Re: help on getting NF
Have you tried with SP analysis which is available in cadence spectre? There is a option of NF(Noise figure) analysis and u can check the result .

Posted to RF Design (Forum) by Analog Design on Tue, May 10 2011
How to design delays for analog pulse(nsec)
Hi , I wan to give some delays to analog pulses whose pulse width is in nsec range . So how to do it? Can anyone help me?

Posted to RF Design (Forum) by Analog Design on Wed, Apr 20 2011

Page 1 of 4 (35 items) 1 | 2 | 3 | 4 | Next >

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