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 Community Search 

Page 1 of 3 (21 items) 1 | 2 | 3 | Next >
  • How to handle pre defined generated clocks in .libs.
    Hi,   In the .libs, generated clock statements help defining the internal clocks being used in the entire design. When the .lib is design, internal clocks are reported or defined with the hierarchy of its instance, with a lot of complex naming conventions. Is there a way to control the naming conventions..  For example   ...
    Posted to Logic Design (Forum) by sureshm on Fri, Jan 4 2013
  • Any comments on the RC Physical Timing co-relation with EDI?
     Dear All, I have the database, which is physical optimized using the EDI flow & I want to further optimizations to reduce the slack, which i think is difficult in EDI, I thought of picking up RTL physical flow for further optimization. I tried to compare the timing of the same design in RC Physical. But i see a humoungus difference ...
    Posted to Logic Design (Forum) by sureshm on Tue, May 8 2012
  • Difference Between PLE, Spatial, Physical
    Hi All,   Can some one be able to explain, the fundamental differences between PLE,Spatial, & Physical of RC flows and the advantages over the other.  In my View,  PLE, Only requires Cap Table as an additional input, which will be used to estimate the net RC from Cap table instead of LEF.   How is the net length of the ...
    Posted to Logic Design (Forum) by sureshm on Tue, May 8 2012
  • Re: placeDesign runTime is 90+ Hrs.
    Hi Gopi, below are the few experiments that you can chose to implement.. 1)  Run the placement without any constraints ..!! That gives you the best area ... !! 2)  Run the placement with Rectangular DEF ( this gives a picture whether the block shape is a problem) 3)  Try the option of Breaking the Block size into manageable ...
    Posted to Digital Implementation (Forum) by sureshm on Tue, Mar 6 2012
  • Re: placeDesign runTime is 90+ Hrs.
     Hi gpremala,     There are multiple inputs you might want to check in the logfile & design partioning .. !!     to me , 2 M instances & 400 memories are bit on a high side to approach for Top-Down Flat Methodology.    May I know the below items to understand the constraints of your design/block ? ...
    Posted to Digital Implementation (Forum) by sureshm on Sun, Mar 4 2012
  • Re: RC synthesis flows
    Hi gh,  When i am doing Zero WL for nets, I am not enabling the PLE Synthesis. Infact, we did couple of experiements with the block sizes and the nature of the clocks, finally came to an experimental number that worked with most of the designs/blocks  of our chip.  PLE with 5-10% of clock frequency is almost giving the similar ...
    Posted to Logic Design (Forum) by sureshm on Sat, Feb 25 2012
  • Re: RC synthesis flows
    Hi gh, Thanks for the answer !!  You are right, RC template scripts are mainly feature driven, unlike DC provides the goal driven template ( best fit-in template for the given target accepted by most of the designers ) I am currently using 20% higher frequency with no wireload model and an uncertainity of 250ps ( blanket) for all the ...
    Posted to Logic Design (Forum) by sureshm on Sun, Feb 19 2012
  • RC synthesis flows
     Dear all, The question may be quite trivial for many out in this forum .. .i would like to discuss more of a methodology related  question with respect to RC tool usage ...for synthesis .!!!  What are the several Synthesis flows recommended by RTL compiler?   Not all designs are computational intensive ...
    Posted to Logic Design (Forum) by sureshm on Sat, Feb 4 2012
  • Issue with the # clocks while synthesizing DW02_mult_4_stage component
    Hi all,    In one of the design,  DW02_mult_4_stage has been used and multiple clocks ( 2 clocks from the top module -- mux convergence of two clocks ) are being fed to this instantiation... while synthesize -to_generic phase of RC synthesis, Tool issues the below Error Error   : The retimeable flops are clocked with ...
    Posted to Logic Design (Forum) by sureshm on Mon, May 23 2011
  • Identifying Half Cycle paths in the design
    Hi all, Although it may sound very trivial task, I would like to get all the half-cycle paths present in my  design, which may go for the review, using RTL ? Any hints in achieving this task ?  Also,  if there is equivalent way of  getting attributes to the timing paths like we have it in pt_shell?? Thanks suresh
    Posted to Logic Design (Forum) by sureshm on Mon, May 23 2011
Page 1 of 3 (21 items) 1 | 2 | 3 | Next >