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 Community Search 

Page 1 of 2 (11 items) 1 | 2 | Next >
  • DFM issues
     Dear Brian Hope you are doing fine and well , I would just like to learn a few more tips (with your help of course). 1. I am trying to put multiple vias on metal contacts. 2. I also want to increase the width of the metal wires by defining a "Non-Default-Rule" in the encounter tool . Both these options are invoked in the ...
    Posted to Digital Implementation (Forum) by BraveHeart on Sat, Jul 28 2012
  • license issues
    Hi  I am experiencing certain problems and licensing issues If any one could help I shall be extremely thankful, I have been getting  LMF-02018 for VERILOG-XL, although I have 5 licesnses in my license.lic file but when I run virtuoso and intiate verilog envoinment I get the above mentioned error.   I shall be very thankfull if ...
    Posted to Digital Implementation (Forum) by BraveHeart on Fri, Jul 20 2012
  • Re: Slotting problems
     Dear Brian thanks for the prompt reply, I am following the complete flow of encounter, By "Without physically connecting it to anything" I meant that I see multiple vias rather an array of 8 via's lying on the power rail but the via's are not connecting anything, they seem to be redundant, the question being why has ...
    Posted to Digital Implementation (Forum) by BraveHeart on Fri, Jun 15 2012
  • Re: Slotting problems
     Dear Brian Hope you are doing well, I am sending you a slide with questions in it.. Although i do understand the science behind the issues I am facing for example long metal wires have to be broken into pieces so that we have uniform spans after a number of grains to cater for charge accumulation, what I dont understand is how can Encounter ...
    Posted to Digital Implementation (Forum) by BraveHeart on Wed, Jun 13 2012
  • Generating LEF from layout view
     Hi all! I have been trying to export LEF from standard cells layout in order to use that LEF file in Encounter for automatic PnR. From virtuoso I select File -> Export -> LEF and fill the form appropriately but the lefout.log is giving a warning on metal 4 as shown below: Warning (OALEFDEF-50144): NONDEFAULTRULE: ...
    Posted to Custom IC Design (Forum) by BraveHeart on Tue, Jun 12 2012
  • Re: Slotting problems
     Dear Brian Thanks allot for the useful information and the video. One other enquiry is that if we have a long wire and our DRC rules dont allow that how can we break the wire and insert a different metal in between. for e.g we have a wire length greater than 400 microns and our DRC rules dont allow that then we should insert jumpers in a ...
    Posted to Digital Implementation (Forum) by BraveHeart on Thu, Jun 7 2012
  • Re: Slotting problems
     Thanks Brian for the help... just a few more questions 1. How can we input the DRC file in Encounter so that encounter respects our rules while placing and routing. 2. I was looking at the Edit->wire->edit and it has a "wire group tab" , although I havent tried it yet but it did not seem to solve my slotting issues but the ...
    Posted to Digital Implementation (Forum) by BraveHeart on Tue, Jun 5 2012
  • Slotting problems
     Hi, 1. I was interested in knowing how can we slot wide metal connects in our automated flow of encounter, I have found an option in place and route, its a guide file which is a text file but that is an  option which is not viable. 2. How can I increase the width of the routing metals. Thanks in advance Aj
    Posted to Digital Implementation (Forum) by BraveHeart on Mon, Jun 4 2012
  • Re: How to perform Post-Layout simulations using UltraSim for Black-Box Cells?
     Hi Quek, Thanks for the post. Actually I have not used AMS before. Before AMS people were doing mixed signal post-layout simulations using ultrasimVerilog, so i should be able to do that as well. I tried with ultrasimverilog and spectreverilog to carryout postlayout simulations but i am getting following errors. The design doesnot have ...
    Posted to Custom IC Design (Forum) by BraveHeart on Fri, Oct 28 2011
  • Re: How to perform Post-Layout simulations using UltraSim for Black-Box Cells?
    Hi Quek Thanks for your reply. I specified the dpf file as per your advice and the simulation has completed successfully and a graph is also plotted but results are not correct! Actually ultrasim is not able to find the 'INVXL' subcircuit. (which is Artisan's standard cell). Here is the message: Notic from UltraSim in ...
    Posted to Custom IC Design (Forum) by BraveHeart on Wed, Oct 26 2011
Page 1 of 2 (11 items) 1 | 2 | Next >