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 Community Search 

Page 1 of 1 (5 items)
  • Referencing symbols with buses during SpiceIn
    I am trying to import a spice netlist using SpiceIn, and one of the instances in the netlist references a cell in one of my libraries.  I have setup a device_map to has the port ordering and breaks up the bus.  The symbol view of this cell has a bus, so when I run SpiceIn, I get the error message: "Found a terminal name mismatch, ...
    Posted to Custom IC Design (Forum) by brianzimmer on Mon, Feb 4 2013
  • Mixed Signal Simulation Question
    Hi, I have been using mixed signal simulation to test a SRAM design and it works great. I have a Verilog-AMS testbench driving the inputs and validating the outputs, and use the AMS simulator with Ultrasim as the solver and OSS as the netlister. My problem is that I would like to use this same setup to run the same simulation on the ...
    Posted to Custom IC Design (Forum) by brianzimmer on Thu, Jul 14 2011
  • Re: Spaced-based router
    Here is the message: M1 vertex must not be connected to two short edges with length
    Posted to Custom IC Design (Forum) by brianzimmer on Sun, Feb 27 2011
  • Re: Spaced-based router
    My version is: sub-version IC6.1.4.500.9 I tried adding various constraints myself pertaining to edge width, but nothing seemed to prevent this. Do you have any idea what rule would prevent something like this?
    Posted to Custom IC Design (Forum) by brianzimmer on Sun, Feb 27 2011
  • Spaced-based router
    Automatic routing is producing many DRC errors by not aligning wires with pins and/or vias. I've tried every routing setting/technology file constraint to prevent this but am at a loss. Any ideas? Thanks, Brian
    Posted to Custom IC Design (Forum) by brianzimmer on Sun, Feb 27 2011
Page 1 of 1 (5 items)