cadence RTL compiler...WNS (Worse Negative slack)
Am synthesizing my HDL code using cadence RTL compiler. Am getting a slack of -14586 ps my clock was 10 ns.
i need to optimize my slack to a small positive value, and my critical path is between a reg to reg (C2C).
doing this i need to apply some constraints na, i have applied output
delay, input_delay constraints, ...