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Page 1 of 1 (4 items)
  • Re: RE: RTL compiler inner clock definition
     Hi! Thank you for the answer. In details, i have incoming DS-encoded data (two signals -SIN and DIN). According to the standard of DS-encoding, clock signal for this data can be produced by XORing  SIN and DIN. So, my project contains XOR component for this operation. On the output of XOR i define clock in the manner, i ...
    Posted to Logic Design (Forum) by EvgeniySUAI on Sun, Feb 20 2011
  • Re: RE: RTL compiler inner clock definition
     I'll try, thank you =) Evgeniy
    Posted to Logic Design (Forum) by EvgeniySUAI on Wed, Feb 16 2011
  • Re: RTL compiler inner clock definition
     Thank you very much for the answer. For me it's very important to learn how to define clocks on design inner signals. It was the requirement for my project.  So i did this in the following manner: set C_D [define_clock -name CLOCK_D -domain d_5 -period 10000 [find /designs/upper_prj/inner_comp -pin q]] RTL compiler did not tell ...
    Posted to Logic Design (Forum) by EvgeniySUAI on Tue, Feb 15 2011
  • RTL compiler inner clock definition
     Hi developers! :) I've faced with problem with defining of timing constraint in RTL Compiler. In my design inner clock is generated based on signals from two input pins (xor on two signals actually).  How can i tell to RTL Compiler, that this inner signal is a clock? I tried create_generated_clock, but it allows to define generated ...
    Posted to Logic Design (Forum) by EvgeniySUAI on Tue, Dec 14 2010
Page 1 of 1 (4 items)