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  • Re: veriloga model not being found
    Does anyone have any suggestions? I implemented all the suggestions in this thread but no luck: http://www.edaboard.com/thread267995.html
    Posted to Custom IC Design (Forum) by kristen on Tue, Oct 9 2012
  • veriloga model not being found
    Hi,  I'm trying to instantiate this veriloga FET model http://ptm.asu.edu/postsi.html and i followed the instructions in the pdf to instantiate as a symbol. now when i try to run a simulation, I see the error: ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'veriloga spectre ...
    Posted to Custom IC Design (Forum) by kristen on Fri, Oct 5 2012
  • Re: incorrect extraction issue
    Hi quek - the result is "yourfile.scs: ASCII C++ program text".
    Posted to Custom IC Design (Forum) by kristen on Wed, Sep 7 2011
  • Re: incorrect extraction issue
    Quek- thanks, it works now (i had forgotten the parentheses). after copying and pasting the old .scs file into this test.scs file the simulations now run. maybe there was some syntax issue with the old file name. Thanks again.
    Posted to Custom IC Design (Forum) by kristen on Tue, Aug 30 2011
  • Re: incorrect extraction issue
    Hi Quek- thanks, I have been trying to get some support from Cadence directly but so far have not heard anything. I had one last idea i wanted to try, making a completely new symbol/spectre object (following your instructions precisely) and then instead used a new .scs file (all with the consistent name "test" that consists of the ...
    Posted to Custom IC Design (Forum) by kristen on Mon, Aug 29 2011
  • Re: incorrect extraction issue
    Quek - the version is 7.1.1.169.isr10. thanks again for all your help.
    Posted to Custom IC Design (Forum) by kristen on Thu, Aug 25 2011
  • Re: incorrect extraction issue
    Quek, a. the line is I6 (0 net4 net2 net28) 100GHz_half_backup which looks correct to me. however when i put in a different subcell (like if i make a schematic and put the symbol view in, the input.scs is populated with the model file). b. the switchview list is: spectre cmos_sch cmos.sch schematic veriloga the stopview list is: ...
    Posted to Custom IC Design (Forum) by kristen on Thu, Aug 25 2011
  • Re: incorrect extraction issue
    Quek, a. yes, i have added the .scs file as a model file. b. it is "Analog". c. see attached. Thanks,
    Posted to Custom IC Design (Forum) by kristen on Wed, Aug 24 2011
  • Re: incorrect extraction issue
    Hi quek, thanks again for your reply. i have the same error as i did before, after following your procedure. some quick clarifications though, do i instantiate the symbol view or the spectre view? i tried both with both yielding the same results. i also noted that changing the model name in the cdf to an incorrect name doesn't ...
    Posted to Custom IC Design (Forum) by kristen on Wed, Aug 24 2011
  • Re: incorrect extraction issue
    Hi Quek, thanks again for your reply. I was mistaken, the issue is in my input.scs file - but my guess is it's not reading my extracted.scs file correctly? the error I get, when i use either a symbol view or spectre view of the subckt, is : ERROR(SFE-678) "input.scs" 15: statement is not in spectre form. use 'simulator ...
    Posted to Custom IC Design (Forum) by kristen on Tue, Aug 23 2011
Page 1 of 2 (18 items) 1 | 2 | Next >