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Page 1 of 12 (116 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »
  • Re: external_driver_input_slew VS set_input_transition
     "external_driver_input_slew" isRTL compiler attribute, the "set_input_transition" is SDC command which is generic , since RTL compiler supports both native and SDC commands both acn be used.  they ae used to specify the slew of the input signal at the  input port. :) i mean both of them. Hope this helps.
    Posted to Digital Implementation (Forum) by gops on Wed, Feb 5 2014
  • parallel termination
    While using parallel resistance termination, we will put Rt same as Z0, right. So inshort the voltage across the parallel resistor will be half of the voltage right? but in real its not half of the voltage. Please tell me how this is happening
    Posted to PCB Design (Forum) by gops on Tue, Oct 22 2013
  • route follow pins inside a block ring.
    I have a softblock in my design. I want  1) create a block ring for the block "A" and the core  ring for other modules skipping the blobk "A". I tried to do this by creating a fence, but encounter don't exclude fence, it dumps an error to chech placement status of fence :( 2) I want to create a separate stripe ...
    Posted to Digital Implementation (Forum) by gops on Fri, Jul 19 2013
  • Can I use just my top metal to create the entire power rings and strap
    Hi, Can I create the neite power structure, I mean both horizontal and vertical lines of core rings, vertical strips and horizontal power stripes using a single metal ( top metal). Is this a right methedology to follow?   I just want to use top metal for power structure. So Can I create the entire power structure using a single metal ...
    Posted to Digital Implementation (Forum) by gops on Fri, Jun 28 2013
  • can CTS help me with following issue?
    In my design I have an SDRAM controler which operates at 100 MHz(10ns). Along with the adddress,data  and control signals, the SDRAM controller provides the clock to the external Memory chip form through IO pad. Now I have some issue with meeting the timing of my design under the following scenario. Assume a read signal is generated by ...
    Posted to Digital Implementation (Forum) by gops on Fri, Jun 7 2013
  • Re: how max_sink_trans value is going to affect the timing of my design
     HI Kari,   thank you very much for the reply.Can you clarify the following queries pls. 1) in the library there is a default_max_trans value .is this applicable for both "D" pin and "clk" pin of the flip flop in the library? or just for "D" pin.   2) Can you pls elaborate on how the ...
    Posted to Digital Implementation (Forum) by gops on Fri, Mar 29 2013
  • how max_sink_trans value is going to affect the timing of my design
     Max_Sink_trans value specifies the clock slew, can some one please let me understand how it is going to affect the timing of my design? Please let me know if it has to be less than the max_transiton_delay in liberty file? or the max_transiton_delay is for the Dpins of the flip flops and max_sink_trans is not dependent on the transtion delay ...
    Posted to Digital Implementation (Forum) by gops on Wed, Mar 27 2013
  • CTS and timing analysis for generated clock
    I have a clock scenario as shown below.  I have defined the B, A as clocks and X as generated clock. In my design X is 300KHz and A is 200 MHz and B is 50 MHz. Sel 2 will switch on the fly during the chip opreation. ie the FFs driven by CLK needs to be run at 300KHz initially and soon after a period it will switch to either 200MHz or 50 MHz. ...
    Posted to Digital Implementation (Forum) by gops on Fri, Feb 1 2013
  • Does clock muxing needs special attention while CTS file creation
    I have a  generated clock, which is muxed with global clock in my design. I have set the generated_clock attribute in my design. How should I handle this for CTS
    Posted to Digital Implementation (Forum) by gops on Wed, Jan 30 2013
  • how encounter handles max_skew value during CTS
    Can some one clarify the following for me. Does encounter optimizes the skew between any two flipflop under the same clock domain for the specified skew value or does it optimizes the skew between the lanuch and capture flops only.What the design requirement to give a more stringent skew value. Is it just to avoid the porblem of the fast datapath ...
    Posted to Digital Implementation (Forum) by gops on Wed, Jan 30 2013
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