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Page 1 of 1 (6 items)

EDA360: Enlightenment for Silicon Test
At a macro level EDA360 is about driving the semiconductor industry toward sustainable differentiation. It represents a Cadence mission to help its customers' customers achieve industry leadership and profitability through enabling technologies, methodologies, and services. Ultimately it is a charter for driving a global ...

Posted to Logic Design (Weblog) by Edward Malloy on Fri, May 21 2010
Enabling Profitable Silicon Production: A Learning ‘Neural’ Network for Yield Ramp
It can not be overstated that the continued health of the chip industry hinges on profitable nanometer production, which depends on yield ramp and yield gap closure. The widening yield gap -- the difference between actual and predicted yield -- and its impact on profitability has far-reaching implications. This fundamental challenge ...

Posted to Logic Design (Weblog) by Edward Malloy on Thu, Apr 29 2010
Logic Design and Test Design: Do they need each other?
Cadence has moved from traditional methods and product offerings for silicon test in favor of a new direction, which answers the title question. In 2008, Cadence recognized that while the Encounter Test product had outstanding quality of results, ease-of-use was lacking. What was perhaps most important was the recognition ...

Posted to Logic Design (Weblog) by Edward Malloy on Sat, Apr 17 2010
Power Management for Test: A Means of Addressing False Failures
Engineering teams are tracing test failures back to IR/voltage drop during test mode. These false failures are impacting yield, profitability. We consider this to be a power management issue for test mode and should be approached as early as front-end design and carried through ATPG and pattern/vector analysis and sign-off. ...

Posted to Logic Design (Weblog) by Edward Malloy on Thu, Oct 23 2008
Test (and Diagnostics) ... it is now a "Value Add" Operation (how are we measuring up?)
A quote from Defect and Fault Tolerance (DFT) 2008 Symposium Key Note Speaker – Phil Nigh, IBM, PhD Carnegie Mellon University: “The role of IC testing is changing – from being viewed as mainly a non-value (cost) operation – to one which provides additional value to products. Historically, the role of Test was to ...

Posted to Logic Design (Weblog) by Edward Malloy on Mon, Oct 13 2008
Quality of test patterns ...which metric is most effective for detecting defective chips?
With lower process geometries and exponential growth in test complexities, associated costs (risks), and aggressive DPPM goals (test escapes): 1) Are today's fault models sufficient to enable defect detection? What are the most common reasons for field escapes 2) Are there any concerns of over-testing due to pessimistic or ...

Posted to Logic Design (Weblog) by Edward Malloy on Tue, Sep 23 2008

Page 1 of 1 (6 items)

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