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 Community Search 

Page 1 of 2 (13 items) 1 | 2 | Next >
  • Re: Move Clock Tree buffers after Integrated clock gate cell in clock tree
    If the integrated clock gating (ICG) cell is capable of directly driving all it's leaf cells without any max cap, tran or fanout violations, normally you would not save any power by moving the ICG tap off point further up the clock tree. Think of it this way, if the main clock was going to be routed there anyway what power are you going to ...
    Posted to Digital Implementation (Forum) by fitz on Wed, Jan 30 2013
  • Re: grep
    I find that parsing the .mtarpt.gz file that is used for the timing debug is the easiest  way to get simple start,  end,  slack reports. report_timing -machine_readable -max_points 50000 -max_slack 5.00   > ${DATE}/${DESIGN}_2_preCTS/${DESIGN}.mtarpt.gz  gzip -cd *.mtarpt.gz | egrep "BEGINPT |ENDPT |SLK ...
    Posted to Digital Implementation (Forum) by fitz on Thu, Jan 24 2013
  • Re: short circuit problems in P & R
    If there is any active circuitry on the cell row I would be very wary of deleting either of the nearest power via stacks completely. That may lead to static and / or  dynamic  IR drop  issues, local voltages lower than your worst case timing library will model correctly. Finding IR drop problems at the last minute before tape out ...
    Posted to Digital Implementation (Forum) by fitz on Mon, Nov 12 2012
  • Re: short circuit problems in P & R
     Two possible solutions A) pre-place filler cells under all of your vertical power stripes to prevent standard cell placement  in the power via stack shadow. B) reduce the size of the power via stack with  addStripe option -max_via_size   Shawn
    Posted to Digital Implementation (Forum) by fitz on Tue, Nov 6 2012
  • Re: How to add tap cells
     "addWellTap" is used to pre-place the initial welltap array, what you are looking for is "addEndCap" Shawn
    Posted to Digital Implementation (Forum) by fitz on Wed, Oct 24 2012
  • Re: Constraining cell placement
     createInstGroup & addInstToInstGroup  - if your current logical heirarchy does not reflect the required grouping.  createSoftGuide  & setPlaceMode -softGuideStrength will cluster your placement. Shawn
    Posted to Digital Implementation (Forum) by fitz on Wed, Oct 24 2012
  • Intel Xeon E5-2690
    Are any of the EDI algorithms / stages  optimized for the new  Intel Xeon  cpu's ? For placeDesign + optDesign -preCTS I am only seeing  a 7% runtime improvement. E5-2690 14hours  vs  X5680 15hours probably due to the 1600 vs 1333 mem speed. According to Intel most of the improvements are in the FPU. Other FP ...
    Posted to Digital Implementation (Forum) by fitz on Wed, Oct 17 2012
  • Re: Regarding clock spec file
    Our vendor has strict technology node dependant SinkMaxTran & BufMaxTran rules. The early / late clock derating factors used to calculate On Chip Variation are characterized within these input transition boundaries. Break the clock input transition rules and your STA timing margins may not be valid. ( not a warm fuzzy feeling at tapeout ...
    Posted to Digital Implementation (Forum) by fitz on Thu, Jul 19 2012
  • Re: Regarding spare cells
    Leakage current, compare the leakage current on a filler vs. standard cell. The lower tech nodes tend to fill first with large decoupling caps then the smaller filler cells. Shawn 
    Posted to Digital Implementation (Forum) by fitz on Wed, Jul 18 2012
  • Re: Regarding dont_touch and dont_use_cell
     Use dont_touch only on instances and dont_use only on cell types , and you will never see this conflict. Shawn
    Posted to Digital Implementation (Forum) by fitz on Mon, Jul 16 2012
Page 1 of 2 (13 items) 1 | 2 | Next >