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 Community Search 

Page 1 of 1 (9 items)
  • Re: CDB to OA Conversion: Layout Issue
    Hi Andrew, I see what you mean by converting to the new prBoudary object. However, I could still find prBoundary/drawing on the OA layout, on top of the prBoundary/boundary which was already converted to the prBoundary object. So is there any condition for the conversion to happen? In the CDB DB, only prBoundary/drawing layer was used.  I ...
    Posted to Custom IC Design (Forum) by sebastion on Tue, May 7 2013
  • Re: CDB to OA Conversion: Layout Issue
    Hi, I noticed that the prboundary/drawing [layer/purpose] layer in CDB got converted into prboundary/boundary in OA, through cdb2oa conversion. This has caused errors in LVL. Is there anyway we can disable the layer purpose conversion in cdb2oa? What I mean is that keep the purpose to remain the same after the conversion. Thanks. 
    Posted to Custom IC Design (Forum) by sebastion on Mon, May 6 2013
  • Re: CDB to OA Conversion: Layout Issue
    We have found the root cause! It is due to the OA techlib version that is older than its CDB counterpart. After switching to the later version of OA techlib, all the weirds things went away. :) @Colin: I have tried to run the translator without -mapviaparams switch, it caused more warnings and did not convert the vias correctly. So I ...
    Posted to Custom IC Design (Forum) by sebastion on Thu, May 2 2013
  • Re: CDB to OA Conversion: Layout Issue
    Thanks for sharing, Colin. We got the PDK in OA version straight from the foundry and the design is referencing to the OA PDK. May I know what makes you think that the "-mapviaparams" switch is the problem?  Thanks. 
    Posted to Custom IC Design (Forum) by sebastion on Thu, May 2 2013
  • Re: CDB to OA Conversion: Layout Issue
    Thanks, Andrew, for the quick reply. I suppose I need to talk to the customer support.  There were a few warnings in the log file, but none of them related to the layers I am dealing with. Here I listed down the warnings I have: CDBOA-517, CDBOA-518 and CDBOA-639. I can provide the elaboration if you are interested.  At first, I ...
    Posted to Custom IC Design (Forum) by sebastion on Wed, May 1 2013
  • CDB to OA Conversion: Layout Issue
    Hi, Cadence version: IC6.1.5 Lately, we have been converting our design database from IC5 to IC6, using cdb2oa script, that was shipped along with IC6. We managed to convert the database without any error. The schematic in OA matched perfectly to its CDB counterpart, but not for the layouts. Most of the layouts were converted correctly. Only a ...
    Posted to Custom IC Design (Forum) by sebastion on Tue, Apr 30 2013
  • Re: Unable to plot phase noise
     Hi Andrew, We upgraded the subversion to 5.10.41.500.6.143 and we are able to plot the phase noise (from pnoise jitter option). Thanks. However, we ran into another problem. In this subversion, we could not run the simulation in GUI mode.The simulation can be carried out by running runSimulation in netlist directory. The error messages ...
    Posted to Custom IC Design (Forum) by sebastion on Fri, Jul 23 2010
  • Re: Unable to plot phase noise
    Thanks for the quick reply, Tawna & Andrew. Tawna: I am currently using 5.10.41.500.6.138 and I did not use any + or - sign for the nets. My setup is shown as follow: simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=65.0 \     tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 ...
    Posted to Custom IC Design (Forum) by sebastion on Thu, Jul 22 2010
  • Unable to plot phase noise
    Hi, After running pnoise: jitter analysis, I wanted to plot the phase noise by choosing: Direct Plot Form => pnoise jitter => Phase Noise => dBc => Plot I got some error messages shown as follow: *Error* flip: can't handle flip(nil) *Error* flip: can't handle flip(nil) *Error* flip: can't handle ...
    Posted to Custom IC Design (Forum) by sebastion on Wed, Jul 21 2010
Page 1 of 1 (9 items)