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  • Register Classes for SystemVerilog OVM
    Hi, I am uploading a register class, which can be used for modeling hardware registers. I am uploading the source code and examples on how to run it. I also have a user guide which has all the APIs listed and explained. The user guide is ARV.pdf in the attached tar file. I have named the class ARV, which stands for Architect's Register View. ...
    Posted to Functional Verification Shared Code (Forum) by AnilRaj on Tue, Sep 9 2008
Page 1 of 1 (1 items)