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 Community Search 

Page 1 of 2 (13 items) 1 | 2 | Next >
  • Verilog-A Monte-Carlo simulations
     Hi all,  I would like to performe Monte-Carlo simulations by using my own transistor model developped in verilog-A language.  For this, I added the line below in the code in order to vary the parameter "CMC" (CMC is a new parameter) (*cds_inherited_parameter*) parameter real CMC=0.0;   also in the file.scs I ...
    Posted to Custom IC Design (Forum) by eppo on Thu, Nov 22 2012
  • Re: MMSIM 111 vs MMSIM 711 veriloga compilation
     Thaanks you Andrew, Effectively, it's a matter of a plateform. i run actually on 32bit.  Regards,   @+   
    Posted to Custom IC SKILL (Forum) by eppo on Wed, Jan 18 2012
  • MMSIM 111 vs MMSIM 711 veriloga compilation
    Hi all, I have a problem with the MMSIM 111 package. 1- I can't perform simulation with the turbo mode. 2- I have a warning with the veriloga code of my component ==> ''veriloga Diagnostics: warning exist in veriloga text of cell SET. Warning: Host inlinsa srv011 does not appear to be a cadence supported linux ...
    Posted to Custom IC SKILL (Forum) by eppo on Tue, Jan 17 2012
  • Verilog-A to .lib transition
     Hi All, I have wrote Verilog-A transistor model and want to perform simulation with tabular method. For this, I need to convert my model to .lib file to improve simulation time.  Anyone have an idea to do this.  Thanks, Regards   
    Posted to Custom IC SKILL (Forum) by eppo on Wed, Sep 14 2011
  • Re: Convergence Problems with spectre
     Hi Andrew, In fact it is a Verilog-A transistor model . The circuit I'm trying to simulate is two transistors in series. Indeed I haven't problem with the DC simulation (Id-Vds) of a single transistor, but I have a warning on one line of code that say''dependencies on thought Passed array arguments ignored. Cdn cause ...
    Posted to Custom IC SKILL (Forum) by eppo on Mon, Sep 27 2010
  • Re: Convergence Problems with spectre
    I do not know why when I post the message does not appear completely
    Posted to Custom IC SKILL (Forum) by eppo on Fri, Sep 24 2010
  • Re: Convergence Problems with spectre
    Hi, I enclose a verilog-A code with the last post code, but it does not appear. // Function that calculates current analog function real Icourant1; input P,Gamaid,Gamadi; real P[-20:20],Gamaid[-20:20],Gamadi[-20:20]; real Ptotal; integer n; begin Ptotal=0; for(n=-20;n
    Posted to Custom IC SKILL (Forum) by eppo on Fri, Sep 24 2010
  • Re: Convergence Problems with spectre
    Thank you Quek for your answer. Indeed, in DC simulation I have 3 same warning but it simulates : Line 160 : Warning: dependencies passed throught array arguments ignored. can cause potential convergence problems. I think that is the problem of convergence (warning) that creates a problem in transient simulation. Line 160 ==> ...
    Posted to Custom IC SKILL (Forum) by eppo on Fri, Sep 24 2010
  • Re: Convergence Problems with spectre
    Thank you Quek for your answer. Indeed, in DC simulation I have 3 same warning but it simulates : Line 160 : Warning: dependencies passed throught array arguments ignored. can cause potential convergence problems. I think that is the problem of convergence (warning) that creates a problem in transient simulation. Line 160 ==> ...
    Posted to Custom IC SKILL (Forum) by eppo on Fri, Sep 24 2010
  • Re: Convergence Problems with spectre
    Thank you Quek for your answer. Indeed, in DC simulation I have 3 same warning but it simulates : Line 160 : Warning: dependencies passed throught array arguments ignored. can cause potential convergence problems. I think that is the problem of convergence (warning) that creates a problem in transient simulation. Line 160 ==> ...
    Posted to Custom IC SKILL (Forum) by eppo on Fri, Sep 24 2010
Page 1 of 2 (13 items) 1 | 2 | Next >