Allegro PCB SI - via model errors
Topology extraction - probe. Simulation fails vias due to via model errors.
Tried the board simulation in 16.3, 16.5, 16.6 errors in all attempts. Rexacted the via models from the board file, failure.
Moved to a different box to run the simulations, there were no errors.
Differences between systems - Windows 7 vs. ...