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Page 1 of 2 (12 items) 1 | 2 | Next >
  • Re: Using RTL compiler PLE with DEF flow
     By the way, I only have RC200.Do I need other feature to run DEF flow?  
    Posted to Digital Implementation (Forum) by tompy on Thu, Mar 27 2014
  • Using RTL compiler PLE with DEF flow
    I would like to adapt DEF flow with RTL compiler PLE.   Is there any user guide or manual I can reference with?   And should I get a detailed DEF from backend or I can just take a rough DEF (only information about memory, hard macro, and some high level hierarchical design)?   thanks!    
    Posted to Digital Implementation (Forum) by tompy on Thu, Mar 27 2014
  • Re: unwanted "\" in netlist
     Hi gh:       I check the RTL, it did have indexing issue like wire declaired as [0:0]  or index exceed its width.   Thanks for the remind.   /tompy
    Posted to Logic Design (Forum) by tompy on Tue, Sep 3 2013
  • unwanted "\" in netlist
     Hi:     I am using RC12 and I found after the synthesized netlist is written out, some net names contains "\", ex: \plus_77_14[23]   I use [find / -net \\plus77_14*] and I cannot get this net since RC doesn't really take "\" as part of the net name internally.   I can only find this net ...
    Posted to Logic Design (Forum) by tompy on Tue, Sep 3 2013
  • How to report leaf cell area
     Hi:       I am using RTL Compiler to report my chip area, but I found it doesn't show the leaf cell area and library area (ex:memories with lib file)  ex: dm/dspm/pram0 is a read in memory lib file, but it is missing in my area report file. I have specified -depth to 10 and it is deep enough to report that cell.Do I ...
    Posted to Logic Design (Forum) by tompy on Mon, Dec 19 2011
  • Re: naming on CSA module
     Hi gh:                   Thanks for the help. I did not find this command before you mentioned it.I search for lots of attributes and don't know there is a command for it.                     But I am ...
    Posted to Logic Design (Forum) by tompy on Fri, Jan 7 2011
  • naming on CSA module
     Hi:      I have a datapath module, after synthesize -to_generic, there are some CSA module has been added by RC, which naming is very ugly. Both in module name and instance name. its RTL is :assign  mout_int = smult(coeff,datain);  where smult is a function.  and  its instance name is : ...
    Posted to Logic Design (Forum) by tompy on Wed, Jan 5 2011
  • Re: defined clocks not propagate
     Hi gh: g151 and g152 are synthesized result, not hand-instantiating. its RTL is:   assign clk1_inv = (!scan_mode) ? !clk1 : clk1;   assign clk2_inv = (!scan_mode) ? !clk2 : clk2;   and synthesized result is    INVD0HVT g40(.I (scan_mode), .ZN (n_2));   XOR2D0HVT g151(.A1 (n_2), .A2 (clk2), .Z ...
    Posted to Logic Design (Forum) by tompy on Tue, Oct 12 2010
  • defined clocks not propagate
    I have a design with clocks defined at root.I can use [get_attrbute  propagated_clocks] to get clock propagate at g152/Z, however, I cannot get propagated clock at g151/Z   XOR2D0HVT g151(.A1 (n_2), .A2 (clk2), .Z (clk2_inv));   XOR2D0HVT g152(.A1 (n_2), .A2 (clk1), .Z (clk1_inv));  I can also get propagated clock at ...
    Posted to Logic Design (Forum) by tompy on Tue, Oct 12 2010
  • Re: how to remove constant value flops?
     Hi gh-           after a lot of trial run, I finally find the root cause. I set boundary_opto attribute to false, which will disable constant propagation across hierarchies, thus avoid RC to remove those unused registers. After set boundary_opto to true, those registers are removed.   BTW, ...
    Posted to Digital Implementation (Forum) by tompy on Thu, Jun 24 2010
Page 1 of 2 (12 items) 1 | 2 | Next >