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 Community Search 

Page 1 of 2 (14 items) 1 | 2 | Next >
  • VDD VSS open violations on FULL CHIP boundary
    Hi All,   I see VDD VSS open violations for full chip boundary  . I have done my powerplan correctly and specified all he global nets but i still open vioaltion on the full chip boundary I feel these has false vioaltions , please help me on this verify connectivity summary    Begin Summary      18 ...
    Posted to Digital Implementation (Forum) by bharat kurra on Fri, Oct 18 2013
  • Macro Channels
    Hi All, Is there any utility or script  in encounter to get all the Hard Macro Channel Information. Thanks -Bharath 
    Posted to Digital Implementation (Forum) by bharat kurra on Tue, Sep 4 2012
  • TimeDesign In ETS
    hi , Is there any command in ETS for getting timing summary  (like timedesign in EDI). I need wns, tns, no: of violating paths for seup & hold and for all corners. - Bharath
    Posted to Digital Implementation (Forum) by bharat kurra on Thu, Apr 12 2012
  • Flattening Netlist
    Hi All,     I have a requirement to flatten my verilog netlist . I know the command "saveNetlist -flat" will do that.   But due to certain reasons i cant use that command . Can some one help me in a perl based or tcl based   script to flatten the netlist  by taking the hierachical netlist and top module ...
    Posted to Digital Implementation (Forum) by bharat kurra on Thu, Mar 15 2012
  • Re: Traversing Each Row
     Get the Particular row lowerleft y co-ordinate and match with all std cells lly co-ordinates all the cells which match belong to that particular row
    Posted to Digital Implementation (Forum) by bharat kurra on Sat, Apr 30 2011
  • Traversing Each Row
    How Can we Get the information of all the Cells in a particular Row
    Posted to Digital Implementation (Forum) by bharat kurra on Fri, Apr 22 2011
  • CPF format
    Hi all, My requirement is something like this my tile in onoff and the output ports need to be always on Can someone help me in writing CPF for above requirement so that i can see a attribute of onoff for all the cells in the tile and always on attribute for output ports I have written a CPF by seeing the user guide but i see a error while ...
    Posted to Digital Implementation (Forum) by bharat kurra on Fri, Apr 15 2011
  • Re: Final Insertion Delay of The Tile
     Thanx But with the above command i am not getting the exact No of Buffers Added in the clock Path.....Like if i manually add a clock buffer in the clock path...this buffer is not added to the count am able to get exact No of Clk Buffers with this command llength [dbGet top.insts.cell.name *_S_*] (My clk Buffers are something like ...
    Posted to Digital Implementation (Forum) by bharat kurra on Fri, Oct 8 2010
  • Max Insertion delay
     Hi all, After  building the clock tree i got max insertion delay of around 1700 ps Hi all, In clock.report  i found the flop having max insertion delay then i reported the timing through this flop with this command report_timing -path_type full_clock -from (flop) report_timing -path_type full_clock -to (flop) but alwayz ...
    Posted to Digital Implementation (Forum) by bharat kurra on Wed, Oct 6 2010
  • Re: How to get rectilinear core coordinates
      Not exactly our intention is to draw a shield metal around our tile,we could draw it for rectangular tile by having the core coordinates...if we can get the core cooridinates for a rectilineartile also....our job is done Thanx Bharat kurra
    Posted to Digital Implementation (Forum) by bharat kurra on Wed, Oct 6 2010
Page 1 of 2 (14 items) 1 | 2 | Next >