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 Community Search 

Page 1 of 1 (7 items)
  • Re: Algorithm used for implementation of Division
    You want to know the internal behaviour of a commercial product. Cadence will never publish such a thing.. Division in Verilog "/" is a fixed-point division, from which RTL Compiler generates division hardware by using synthetic operator DIV_UNS_OP or DIV_TC_OP. There are two other synthetic operators DIV_UNS_IEEE_OP and DIV_TC_IEEE_OP ...
    Posted to Logic Design (Forum) by Sporadic Crash on Tue, Jan 7 2014
  • how to identify unique nets connected to preset/clear pins of all FFs in a scope
    I have not been able to find an attribute that shows whether a net in a scope is connected to a preset/clear of FF.  The only way I have found: foreach FF in a scope {  foreach pin of this FF {   if { libpin of this pin is a {async_clear} } { set an async_clear net }   if { libpin of this pin is a {async_preset} } { set an ...
    Posted to Logic Design (Forum) by Sporadic Crash on Tue, Jan 7 2014
  • Re: RC: set_min/max_delay breaks the constrained paths
    I have tried following combinations:  set_attribute timing_no_path_segmentation {set_max_delay set_data_check} / read_sdc <file> ... -> still broken paths. Then I tried  set_attr tim_ignore_data_check_for_non_endpoint_pins true / set_attr tim_ignore_data_check_for_non_endpoint_pins false / with the command above. Still broken ...
    Posted to Logic Design (Forum) by Sporadic Crash on Tue, Mar 26 2013
  • RC: set_min/max_delay breaks the constrained paths
    I have used following command(s) to constraint path delays on FF->FF path: set_max_delay -from $some_flops -to [get_pin inst/in_i*] 8 The path that goes through [get_pin inst/in_i*] ends in a target FF. However when after the SDC command above, when I try to generate a timing report, following message is coming from RTL ...
    Posted to Logic Design (Forum) by Sporadic Crash on Tue, Mar 26 2013
  • Re: gray code
    Hi gh-,  RTL Compiler has no support to control FSM coding style. I vaguely remember even Synplify had a pragma for this (binary, one-hot, gray or Johnson coding). I have done an experiment: Synthesized 9-bit binary counter, and then synthesized 9-bit Gray counter (using CW_cntr_gray) using following coding style: CW_cntr_gray ...
    Posted to Digital Implementation (Forum) by Sporadic Crash on Mon, Oct 29 2012
  • Re: How to get the activity power in Simvision
    Run a simulation (RTL or netlist) and dump your VCD file. In RTL Compiler: read the design (RTL or netlist, the same way as above. If VCD file is generated from RTL, read the RTL. If VCD file is generated from netlist, read netlist). elaborate the design.Then I will show another technique: call the read_vcd command, without ...
    Posted to Functional Verification (Forum) by Sporadic Crash on Wed, Oct 24 2012
  • Re: gray code
    I am interested in Gray coding with RTL Compiler. In the tool following synthetic operators are used: BIN2GRAY_STD_LOGIC_OP, GRAY2BIN_STD_LOGIC_OP, INC_GRAY_STD_LOGIC_OP  Additionally, following ChipWare components are related to Gray codes. CW_inc_gray, CW_gray2bin, CW_cntr_gray, CW_bin2gray  There is no known example how ...
    Posted to Digital Implementation (Forum) by Sporadic Crash on Wed, Oct 24 2012
Page 1 of 1 (7 items)