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Page 1 of 3 (23 items) 1 | 2 | 3 | Next >
  • New Incisive Verification App and Papers at DVCon by Marvell and TI
    If you're an avid reader of Cadence press releases (and what self-respecting verification engineer isn't?), you will have noticed in our Incisive 13.2 platform announcement  back on January 13th that Incisive Formal technology, with our new Trident cooperating multi-core engine, took top billing. But you would have needed to be very ...
    Posted to Functional Verification (Weblog) by Pete Hardee on Thu, Feb 27 2014
  • Ultra Low Power Benchmarking: Is Apples-to-Apples Feasible?
    I noticed some very interesting news last week, widely reported in the technical press, and you can find the source press release here. In a nutshell, the Embedded Microprocessor Benchmark Consortium (EEMBC) has formed a group to look at benchmarks for ultra low power microcontrollers. Initially chaired by Horst Diewald, chief architect of ...
    Posted to Low Power (Weblog) by Pete Hardee on Tue, Feb 12 2013
  • Low-Power Technology Summit Proceedings Now Available
    On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view the material via the Low-Power Technology Summit Proceedings archive, which just ...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Dec 5 2012
  • Perspective on Power: 2012 Survey Predicts 2013 as the Year of DVFS
    The recent Low-Power Technology Summit held at Cadence headquarters in San Jose gave us a great opportunity to take the pulse of low-power design by surveying the attendees. Some of the data we got was expected, but there were a couple of surprises. First, some of the expected stuff. We'd noticed in the last major surveys done almost two ...
    Posted to Low Power (Weblog) by Pete Hardee on Thu, Nov 29 2012
  • Packed House Expected for Cadence Low-Power Technology Summit
    It looks like it might be standing room only for latecomers to the Low-Power Technology Summit at Cadence headquarters building 10 auditorium this Thursday (18 October). Registration has been very strong. I'm expecting a great day -- we have a full agenda covering multiple aspects of low-power design. No longer the sole preserve of designers ...
    Posted to Low Power (Weblog) by Pete Hardee on Tue, Oct 16 2012
  • Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year
    CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012 Worldwide page. Proceedings are published so far from San Jose, USA; Munich, Germany; and ...
    Posted to Low Power (Weblog) by Pete Hardee on Mon, Sep 17 2012
  • Mixed Signals from European Low-Power Designers
    Early summer is a good time to visit Europe.  I was there for the first couple of weeks in July, before most of Europe disappears on vacation. I spent my time mainly with customers in Germany, Ireland and the UK. It's not the weather that makes it a good time to visit - while it was nice in Germany the Northern European summer has been a ...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Jul 25 2012
  • What’s Cool for Low-Power at DAC?
    Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject, there's a lot to choose from at Cadence's booth #1930. Here is a quick guide to ...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 30 2012
  • Low-Power Design? Brian Bailey Gets It
    Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles on the subject of low power design. As he put it: "I doubt if the EDA Designline, or ...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, May 2 2012
  • Cadence Customers to Showcase Advanced Low-Power Designs at CDNLive!
    CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems. ...
    Posted to Low Power (Weblog) by Pete Hardee on Wed, Mar 7 2012
Page 1 of 3 (23 items) 1 | 2 | 3 | Next >