Home > Community > Search
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Community Search 

Page 1 of 2 (12 items) 1 | 2 | Next >
  • Ron of nmos in Cadence for deep triode region of operation
    Hey, Can anyone help me with plotting the on resistance of nmos transistor in Cadence when we do dc analysis. I am trying to understand how ron changes with Vgs voltage. How do we do this plot. Any help is appreciated. Thank you.  
    Posted to RF Design (Forum) by Mohana on Tue, Oct 9 2012
  • SNM calculation for SRAM
     Hey,   I am currently working on SRAM cell. I need to calculate the SNM-read, write and idle for my cell. I have the understanding of what is SNM. But i am not sure on how to plot the butterfly curve for the cell in cadance. Could any1 please help me with this.   Thank you   Mohana
    Posted to RF Design (Forum) by Mohana on Mon, Dec 6 2010
  • Re: Layout help
     Hey Andrew, I tried the option mentioned by you but it didnt work. and also i am unable to view the link that u sent me. Is there any other way that i can access that link?   Thank you Mohana 
    Posted to RF Design (Forum) by Mohana on Tue, Sep 14 2010
  • Re: Layout help
     Hi Andrew,  The transient analysis is not right. if the analysis was working right then the percentage of progress wouldnot be 2%, it would vary.  can you please explain more about the capacitive path to ground? Asha
    Posted to RF Design (Forum) by Mohana on Wed, Sep 8 2010
  • Layout help
     Hi, I am working on LC-VCO. the testbench for the schematic works fine but when i try the testbench for my layout it gives me error with the initial condition. The config mode works for c-only extraction. but when consider the complete paracitics, the transient analysis is stopped because of the error with the initial condition. i have ...
    Posted to RF Design (Forum) by Mohana on Tue, Sep 7 2010
  • Re: problrm in the test bench
     hi Tawna,  I figured out what was wrong. i didnt put in the initial condition to the circuit which was causing me trouble.   thank you for the help.   Asha
    Posted to RF Design (Forum) by Mohana on Mon, Jul 19 2010
  • Re: problrm in the test bench
     hello Tawna,  i am attaching a copy of my spectre.out file and my netlist in this pos. i think this will help u to better analysis my problem  spectre.out file Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator Version 7.2.0.109 32bit -- 6 Dec 2009 Copyright (C) 1989-2009 Cadence Design Systems, Inc. All rights reserved ...
    Posted to RF Design (Forum) by Mohana on Mon, Jul 19 2010
  • problrm in the test bench
    Hii i am working on LC-VCO. the schematic works fine but when i try to make the test bench, the symbol does not work properly when i am doing the transient analysis. i am unsure of what is the problem . can any1 suggest me something where i could go wrong? Asha
    Posted to RF Design (Forum) by Mohana on Mon, Jul 19 2010
  • Re: Insufficient memory
       hi Tawna, I am unable to open the link that was sent by you. Could you please attach that file and email me. My email address is m.ashalathadubasi@my.unt.edu. Thank you very much for your help.Mohana
    Posted to RF Design (Forum) by Mohana on Tue, Apr 6 2010
  • Re: Insufficient memory
     hi Tawna, I am unable to open the link that was sent by you. Could you please attach that file and email me. My email address is m.ashalathadubasi@my.unt.edu. Thank you very much for your help.Mohana
    Posted to RF Design (Forum) by Mohana on Tue, Apr 6 2010
Page 1 of 2 (12 items) 1 | 2 | Next >