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 Community Search 

Page 1 of 2 (16 items) 1 | 2 | Next >
  • NanoRoute stack trace for 28nm Data
     Hi,      I am trying to route the 28nm data (with synopsys standard cell library) using nanoRoute 11.1USR2, but i am not able to complete the routing as nanoroute come out with stack trace and there is nothing much of information in the log file to find the cause for stack trace.             ...
    Posted to Digital Implementation (Forum) by deeps on Wed, Dec 26 2012
  • Re: "Word too long" error while running write_vectors step in Encounter test
     Hi Krishna,              I guess this is issue with linux, there is some limit in linux when considering the hash/length of a variable (may be we can change this limit with some settings but i am not aware of that).                     I also had the same ...
    Posted to Logic Design (Forum) by deeps on Mon, Oct 31 2011
  • Need some SSTA flow details
     Hi,         I was looking at the SSTA flow in ETS and had some doubts. I wend through the SSTA details present in the ETS user guide but wanted to find out more details explanation of the use and requriement of SSTA.              If some one has already evaluated/used SSTA and have ...
    Posted to Digital Implementation (Forum) by deeps on Mon, Oct 31 2011
  • how to validate delay change details reported due to cross talk effect in spice
     Hi,    I am trying to validate ETS101USR2 cross talk anlaysis details with that of spice,         For glitch violations i can pick the victim net and  check the same glitch peak and width in spectre output.              But for delay change details caused by the cross ...
    Posted to Digital Implementation (Forum) by deeps on Wed, Aug 24 2011
  • ETV Vs Spice cell delay Values
     Hi,     I am trying to compare the cell delay details reported from ETS10.1USR1 for a 40nm design with that of spice, but i am finding huge deviations in the cell delays reproted.             for example for a given cell if ETS reports 100ps then in spice for the same cell the delay reported is ...
    Posted to Digital Implementation (Forum) by deeps on Mon, Aug 1 2011
  • Re: Validate CDB noise model file
     Hi Kari & Nigel,         Thanks for your suggestions, i went through the makecdb.pdf and also had used the same "validate_cell_lib" command, But i wanted to know should this be enough or its better we do some kind of spice simulations to find out the quality of the data genrated from make_cdb ...
    Posted to Digital Implementation (Forum) by deeps on Thu, Jul 1 2010
  • Validate CDB noise model file
    Hi All,  I am trying to create a .cdb file using make_cdb utility for some of the custom cells.       Can some one suggest me the best way to validate the created .cdb file.   regards deepak.
    Posted to Digital Implementation (Forum) by deeps on Thu, Jul 1 2010
  • Re: Stacked via violations in encounter power router.
    Hi Kari, I am using verify geometry command to get details of the violations (not Sign off)  I am not sure the reason for this kind of violations, I got some inputs from Cadence support saying that I need to set some variable before creating the power routes (setvar ALLOWOVERLAPINSTACKVIA true) But still there are lot of stacked via ...
    Posted to Digital Implementation (Forum) by deeps on Mon, Nov 9 2009
  • Stacked via violations in encounter power router.
     I am trying to create the power routes using Encounter 9.1  There are lot of memories in the design which has power pins in layer M4  ( design is 8 Metal layer process) i create the stripe in M3 & M7 where in M7 gets tapped to some of the power pins of the memories as the pitch of M7 is such that some of the memory pins does not ...
    Posted to Digital Implementation (Forum) by deeps on Wed, Nov 4 2009
  • Re: Follow rails for empty rows.
       Hi Kari,       I have set the corePinNoRouteEmptyRows to "off" but still its not creating follow rails for some empty,(not at all empty rows, follow rails are created at some places where the rows are empty)          There is no blockage or any kind of ...
    Posted to Digital Implementation (Forum) by deeps on Wed, Aug 19 2009
Page 1 of 2 (16 items) 1 | 2 | Next >