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 Community Search 

Page 1 of 1 (9 items)
  • Simulation settings
    Hi, I am designing an all digital pll using cadence 6.1.4. It is taking about 10 us to lock the output. When I am trying to run my simulation that long it is taking 3-4 days. I tried using aps simulation (errpreset = liberal) instead of spectre and could decrease the simulation time to 1 day. I am also saving only the outputs that are required ...
    Posted to Custom IC Design (Forum) by pmuppala on Wed, Feb 16 2011
  • Re: vhdl behavioral code to schematic conversion in cadence
    I am using just virtuoso 6.1.3. I read in some previous posts that we need to have standard cell library with all the gates pre-declared inorder to import a verilog or vhdl code and use it..
    Posted to Custom IC Design (Forum) by pmuppala on Fri, Nov 5 2010
  • vhdl behavioral code to schematic conversion in cadence
    hi, I implemented a binary search algorithm in vhdl using behavioral description. I imported this file from cadence and created a symbol for this.When i try to add this as an instance in any other schematic and simulate it, it shows an error saying that there is no view of type spectre.. How can i resolve this.. Thanks in advance, Muppala
    Posted to Custom IC Design (Forum) by pmuppala on Thu, Nov 4 2010
  • Re: Skill code for Off Grid errors
    Andrew, Thanks for your time and reply. I will check it in the cadence online support forms. Regards, Muppala.
    Posted to Custom IC SKILL (Forum) by pmuppala on Wed, Sep 8 2010
  • Re: Skill code for Off Grid errors
    Hello Andrew, Thanks for your prompt response.This one worked to get rid-off the error i am getting ** Error** -eval -- undefined function selset.... But when i ran the script with the suggested modifications u told it still shows the off-grid errors. Regards, Muppala.
    Posted to Custom IC SKILL (Forum) by pmuppala on Wed, Sep 8 2010
  • Re: Skill code for Off Grid errors
    Hey Jifang and How, I  am also getting the same problem even when i am selecting all the objects in the cellview. It says:  *Error* eval: undefined function -selset Hey Jifang, can u give me the script which u got , i searched in the sourcelink and could not find any luck. Any help is highly appreciated. Thanks, Muppala
    Posted to Custom IC SKILL (Forum) by pmuppala on Tue, Sep 7 2010
  • Standard Cell Library Design
    I am planning to design a standard cell library for 90nm process using Cadence 6.1.3 version. Can someone help me know how to use the parameterised-cell concept in designing the library. Any reference to useful material or any other form of idea will be highly appreciated.
    Posted to Logic Design (Forum) by pmuppala on Thu, Jul 15 2010
  • Re: Help needed regarding cadence simulation
     @Diablo,     Hey thanks for your time and reply. What u said is a valid point and I will try to minimise probing outputs instead of saving all.  
    Posted to Digital Implementation (Forum) by pmuppala on Mon, Mar 29 2010
  • Help needed regarding cadence simulation
    hey guys, I am using cadence 6.1 . When I am simulating a schematic (big one takes 1 day) , I find that the simulation takes a lot of memory. I deleted the file tran.tran.trn in the simulation folder after my results were obtained but even then, it seems like it takes a lot of memory. Please tell me where else simulation results will be ...
    Posted to Digital Implementation (Forum) by pmuppala on Mon, Mar 29 2010
Page 1 of 1 (9 items)