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 Community Search 

Page 1 of 3 (23 items) 1 | 2 | 3 | Next >
  • SDF Generation Confusion
    Hi, I have been given some SDF that has been generated for min/max write_sdf ../SDF/func.sdf      -precision 6 -max_view func_worst  -min_view func_best  When I look in the SDF file, I see:     (CELL     (CELLTYPE  "SDFFRX1")     (INSTANCE  ...
    Posted to Digital Implementation (Forum) by moogyd on Wed, Nov 7 2012
  • Re: RE: irun: design.v is verilog and verilog AMS
    Hi Tim, Thanks for the ideas 1) This would solve the immediate issue. We are currently not using SV, but will be in future. However, I guess that we would not be mixing wreal and sv in the same file. 2) Extra marks for "thinking outside the box", but no thanks :-) I don't think this solution would make me very popular within the ...
    Posted to Functional Verification (Forum) by moogyd on Thu, Oct 18 2012
  • irun: design.v is verilog and verilog AMS
    Hi, We are migrating to an irun based flow to simplifiy our compile/elab/sim flow, and have a slight issue. We have a file design.v, containing module design. Depending on a define, this can either be a standard digital module, or a WREAL model. i.e. Within the file `ifdef WREAL wreal sig_name;  `endif This issue is that irun uses the ...
    Posted to Functional Verification (Forum) by moogyd on Thu, Oct 18 2012
  • RTL Compiler, Min Libraries and CPF
    Hi, For synthesis (RTL compiler) I define a worst case libraries read_cpf -libraries, and in the CPF I use define_library_set -name my_lib_set _librares {libA_slow.lib libB_slow.lib libC_worst.lib}  i.e. I load multiple worst case librarie (there are actually about 15, from different vendors) I then export the CPF for the backedn. This ...
    Posted to Logic Design (Forum) by moogyd on Thu, Jul 19 2012
  • Re: RTL Compiler: DFT Checks and non controllable/observable I/O
    Hi Douglas, I did not find a solution other than to disable auto-identification as described by Brad.  Steven
    Posted to Logic Design (Forum) by moogyd on Thu, Jul 19 2012
  • Conformal ECO Flow Basic Question
    Hi, I think that understand the basic flow, but these is one issue that causes issues.  I have the current post layout netlist G1 - this is "golden" I generate a new netlist using RTL compler G2 - this is "revised". I can compare G1 and G2 and generate patch files using conformal ECO. There is one major issue, and it ...
    Posted to Logic Design (Forum) by moogyd on Fri, Mar 30 2012
  • Re: RTL Compiler: DFT Checks and non controllable/observable I/O
    Hi Again, Having checked further, this is not what I want.  This attribute only applies to pins, and is intended for internal black boxes. I need something to apply to design ports, and to indicate that a pin is not controllable (even though it is a primary input) Any additonal suggestions? Thanks, Steven
    Posted to Logic Design (Forum) by moogyd on Wed, Feb 1 2012
  • Re: RTL Compiler: DFT Checks and non controllable/observable I/O
    Hi, Excellent - this is just what I'm looking for. Thanks for the quick feedback, Steven
    Posted to Logic Design (Forum) by moogyd on Tue, Jan 31 2012
  • Re: RTL Compiler: Remove Empty Modules
    Hi, Sorry, I seem to have made a mistake. I was informed by the layout engineer (encounter) that there were empty modules, and we both assumed that they were present in the netlist from RTL Compiler to Encounter. Having checked, it seems that this is not the case, and that Encounter is somehow creating empty modules. We need to check why this ...
    Posted to Logic Design (Forum) by moogyd on Tue, Jan 31 2012
  • RTL Compiler: DFT Checks and non controllable/observable I/O
    Hi, I am synthesizing a top level digital block that has interfaces to external pads and to a top level analog block. When I run DFT checks, it assumes that all ports are controllable, which is not the case for the signals from the top level analog block. Is the an attribute I can apply to these ports to indicate that they are not ...
    Posted to Logic Design (Forum) by moogyd on Tue, Jan 31 2012
Page 1 of 3 (23 items) 1 | 2 | 3 | Next >