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 Community Search 

Page 1 of 1 (10 items)
  • Functional Coverage Question
     I have 2 coverpoints.  Each coverpoint has auto generated bins as well as user-defined bins.  In pseudo-code, I will describe them as follows:  cp1:       auto_bins,      userdefined_bin0, userdefined_bin1 ;     cp2:      auto_bins, ...
    Posted to Functional Verification (Forum) by ashfaqh on Sun, Jun 22 2014
  • Re: Simple UVM Bench Issue
    I managed to figure out how to do this on my own. (1)  I declare an int in the Driver class.     protected int my_switch = 0 ;  // default value is zero  (2) I register it in the Driver class as:   `uvm_field_int(my_switch, UVM_ALL_ON) (3)  Then in the test_lib, inside class myTest_x, I use ...
    Posted to Functional Verification (Forum) by ashfaqh on Mon, Oct 10 2011
  • Simple UVM Bench Issue
      I have created a UVM Bench.  I am using INCISIVE_10_20. All components are in place and things are going good.   I have the following: (1) Master Agent (2) Driver (3) Monitor (4) Sequencer (5) test_lib : I specify the particular sequence to use in each testclass (6) Scoreboard    My Driver is driving the ...
    Posted to Functional Verification (Forum) by ashfaqh on Fri, Oct 7 2011
  • Simple UVM Bench Issue
    I have created a UVM Bench.  I am using INCISIVE_10_20. All components are in place and things are going good.   I have the following: (1) Master Agent (2) Driver (3) Monitor (4) Sequencer (5) test_lib : I specify the particular sequence to use in each testclass (6) Scoreboard    My Driver is driving the intended ...
    Posted to Functional Verification (Forum) by ashfaqh on Fri, Oct 7 2011
  • Re: Forcing a VHDL signal from a Verilog Test/Env
    Mickey:  Thanks for your response.  I tried and got the following error msg.  Please suggest.  Thanks,  -Ashfaq    Top level design units:                 ...
    Posted to Functional Verification (Forum) by ashfaqh on Sat, Jul 23 2011
  • Forcing a VHDL signal from a Verilog Test/Env
     I have a Testbench with a DUT which has VHDL and Verilog RTL modules.  The tb_top is verilog.  The test file is a verilog.    From the verilog test, I need to force a signal inside the DUT several hierarchies down.  The signal I need to force is inside a VHDL module.   This signal is not available at the top ...
    Posted to Functional Verification (Forum) by ashfaqh on Thu, Jul 21 2011
  • VHDL Procedure Call from a Verilog Module
    I have a third party encrypted VHDL source (*.vhdp).  I am using ncvhdl to compile this source into a library. But, I want to call the library (components) from a Verilog module as verilog tasks. So, how do I call VHDL procedures (already compiled into a library) from a Verilog module? Thanks, -ashfaqh  
    Posted to Functional Verification (Forum) by ashfaqh on Fri, Aug 6 2010
  • Re: MixedLanguage (Verilog+VHDL) Question
    Mickey: Your suggestion has worked very nicely!  Thank you very much for your help.  I wasn't aware of the $nc_mirror() task which allows VHDL signals to be probed from Verilog module.   I also successfully experimented by calling a user-defined Verilog task() from a verilog island module inside a VHDL top-level DUT -- that ...
    Posted to Functional Verification (Forum) by ashfaqh on Thu, Aug 5 2010
  • MixedLanguage (Verilog+VHDL) Question
     Hello:  I am using  ncsim   09.20-s016.  I have a VHDL DUT.  The testbench top level is VHDL.  But, I have a few Verilog modules in the testbench. From one of the Verilog modules, I want to access (monitor) a signal inside the DUT (VHDL).  For example, if (top.level_1.level_2.sigout_1 == ...
    Posted to Functional Verification (Forum) by ashfaqh on Thu, Aug 5 2010
  • Referencing a VHDL signal from a Verilog Module
     Hello:  I am using  ncsim   09.20-s016.  I have a VHDL DUT.  The testbench top level is VHDL.  But, I have a few Verilog modules in the testbench. From one of the Verilog modules, I want to access (monitor) a signal inside the DUT (VHDL).  For example, if (top.level_1.level_2.sigout_1 == ...
    Posted to Functional Verification (Forum) by ashfaqh on Wed, Aug 4 2010
Page 1 of 1 (10 items)