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 Community Search 

Page 1 of 6 (60 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »
  • Re: RC - read_hdl
    Hi Grasshopper, Thanks a lot for your help. Actually script was reading all the files line by line with read_hdl for each one. I believed that if we define library it will resolve the scope visibility issue, but it didn't.  It works now, after I fixed it as you advised: read_hdl  { include.v a.v ...
    Posted to Logic Design (Forum) by Yemelya on Wed, Jul 31 2013
  • RC - read_hdl
    Hi Everyone, When reading verilog (read_hdl -sv), first file is common variable definitions (like `define and localparam). There is no problem loading this file, however when loading the actual RTL design it cannot recognize the mentioned above variables (Error - undeclared). If the same  variable ...
    Posted to Logic Design (Forum) by Yemelya on Wed, Jul 31 2013
  • analyze_early_rail - ERROR: (ENCPARA-1132)
    When running analyze_early_rail for ""vss" It works well, but for some reason does not work for VBAT. "analyze_early_rail -method static -type net_based -bias_voltage 1.55 -net_voltage 1.1 -volt_limit 0.9 -total_current 20 -pad_location_file { {mosquito_afe_vbat.pp vbat} } -display_IR -net vbat" I got errors ...
    Posted to Digital Implementation (Forum) by Yemelya on Wed, Jul 24 2013
  • RC: to Remove PG pins from a Netlist..
    Hello, There are several Power/Ground pins in the RTL design (and they cross many hierarchies). Given that they require special route in Encounter, to define them as pgpins, this pins have to be removed from the netlist.  During the synthesis, I tried to use “rm” or “set_atrribute ... pgpin”   - ...
    Posted to Logic Design (Forum) by Yemelya on Mon, Oct 22 2012
  • LEC issue - "elaborate" vs. "synthesize -to_generic"
    Hi, When running  LEC on golden-(elaborate) and revise-(synthesize -to_generic) getting one NON-EQ compare point.  The following RC attributes didn't help: set_attribute prune_unused_logic false [find [find / -inst TOP/SUB ] -ignorecase -pin *] set_attribute prune_unused_logic false [find [find ...
    Posted to Logic Design (Forum) by Yemelya on Fri, Oct 5 2012
  • ROM from cells.
    Hi, I’m working with the technology which doesn’t have ROM. So I need to implement it by tie cells or any other way. Does Encounter have a solution for such a case, or may be somebody has an experience with custom (from lib cells) ROM design? Thanks...Boris  
    Posted to Digital Implementation (Forum) by Yemelya on Thu, Sep 27 2012
  • scanReorder limitations
    Hi, How can I set the following constrains to scanReorder procedure:   1.  Scan chains length can NOT change.  2.  Scan chains clocking of the first and the last scan cell can NOT change, or how can I keep them (the first and the last cell out of the reordering, like “set don’t touch” ). Thank ...
    Posted to Digital Implementation (Forum) by Yemelya on Tue, Nov 22 2011
  • 1. rename routed net / 2. add pin
    Hi, 1. Is possible to rename a routed net? 2. How can I add a pin without loadIoFile command? It's an ECO and I need only incremental update. Thanks! Boris
    Posted to Digital Implementation (Forum) by Yemelya on Wed, Aug 24 2011
  • Re: pin location
    Thanks!
    Posted to Digital Implementation (Forum) by Yemelya on Wed, Aug 24 2011
  • Re: pin location
    Oh! I have found it: dbTermLoc
    Posted to Digital Implementation (Forum) by Yemelya on Wed, Aug 24 2011
Page 1 of 6 (60 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »