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 Community Search 

Page 1 of 8 (74 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »
  • Re: creating a bom
    Here's a solution with CIS. Open the page, set your selection filter to parts, draw a window across the page, selecting all parts on that page.   Menu Click > "add to group".    (may have to create the group in CIS part manager first...) Go to CIS part manager, export the BOM from that group.  
    Posted to PCB Design (Forum) by Robert Finley on Tue, Jul 29 2014
  • Re: How to make a Panel Drawing in cadence Allegro editor?
    Consult with your board fabricator.  They should be able to merge separate ODB++ files into your assembly panel before photoplot.   You must avoid losing netlist intelligence (IPC356 or internal ODB++) used for test/verification at pcb fab.  Where I work, we use a fabricator on first-name basis with our assembly house.   Both ...
    Posted to PCB Design (Forum) by Robert Finley on Tue, Jul 1 2014
  • Re: How to make a Panel Drawing in cadence Allegro editor?
    Have your pcb fabricator do this from individual ODB++ files.  They are designing your SMT Assembly panel.   You will need to get the assembly people involved to decide on the panel size (so it fits in their machines) and if they need additional registration holes or fiducials.  
    Posted to PCB Design (Forum) by Robert Finley on Mon, Jun 30 2014
  • Re: PTH/NPTH Drill to Copper feature spacing issue
    If this is part of a footprint, seems like a circular polygon on the RouteKeepout class would permanently solve the problem.  (still trying to figure out what the footprints I use from Samtec do to solve the problem.) 
    Posted to PCB Design (Forum) by Robert Finley on Mon, Jun 30 2014
  • Re: OrCAD PCB Editor - Padstack Designer
    Padstacks are cached in your pcb file.   If you update a footprint symbol to use the new padstack names, you will be able to update your symbols when revising the board file, that will pull in the new padstacks.  If there is a weird reason you need that named padstack back, you can export footprints and padstacks out of an ...
    Posted to PCB Design (Forum) by Robert Finley on Fri, Mar 21 2014
  • Re: Fillets(teardrops)
    Trade ya'.  My MEs are campaigning to senior management on subdividing a high-speed design to 5 individual cards with a passive backplane...and cheap berg headers. Round enclosures with "screw-on caps" take less than a year to certify as explosion proof.  But... Fillets are an old concept. Helped improve yield when the ...
    Posted to PCB Design (Forum) by Robert Finley on Fri, Mar 21 2014
  • Re: How to make FPGA symbol for schematic
    The only time I manually type in pin names is on something with fewer than 6 pins.  Check out the EDABuilder app from EMA-EDA. Zero retyping... From either the Altera BSM file or a spreadsheet. Extracted the pinmap for Intel's 2011-pin Pentium package recently from their datasheet PDF. And, their footprint builder rocks too.   ...
    Posted to PCB Design (Forum) by Robert Finley on Thu, Mar 6 2014
  • Re: How to change the center drill point (black dots)as some other symbol in allegro??
    You're looking at the drill-size check plot of your drill data.  You're getting that, so it looks like you're generating the drill information correctly.You need to add an artwork film that draws the manufacturing drill legend and drill symbol layers, plus the board outline.  It's traditional to add overall board ...
    Posted to PCB Design (Forum) by Robert Finley on Mon, Feb 24 2014
  • Re: [Help] PADS layout to Allegro PCB translation
    Only thing we noticed is the translated symbols left us without DFA or placement DRC boundaries. The translator makes no attempt to reuse existing padstacks.  Just builds new padstacks with a serial number each time.Used our library automation to generate a second library with footprint names matching what we had in PADS (we didn't ...
    Posted to PCB Design (Forum) by Robert Finley on Sat, Jan 4 2014
  • Re: Attaching Different Nets
    I have to think fabricators are calling with questions (and putting the job on hold) when shorted nets aren't specified in the fab drawing notes. If you design power systems with force/sense lines, it is faster/safer to check the sense location if the short is a physical component.  ATE testing of a 120-pin PMIC device with 16-30 ...
    Posted to PCB Design (Forum) by Robert Finley on Sat, Dec 28 2013
Page 1 of 8 (74 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »