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 Community Search 

Page 1 of 7 (70 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »
  • Re: OrCAD PCB Editor - Padstack Designer
    Padstacks are cached in your pcb file.   If you update a footprint symbol to use the new padstack names, you will be able to update your symbols when revising the board file, that will pull in the new padstacks.  If there is a weird reason you need that named padstack back, you can export footprints and padstacks out of an ...
    Posted to PCB Design (Forum) by Robert Finley on Fri, Mar 21 2014
  • Re: Fillets(teardrops)
    Trade ya'.  My MEs are campaigning to senior management on subdividing a high-speed design to 5 individual cards with a passive backplane...and cheap berg headers. Round enclosures with "screw-on caps" take less than a year to certify as explosion proof.  But... Fillets are an old concept. Helped improve yield when the ...
    Posted to PCB Design (Forum) by Robert Finley on Fri, Mar 21 2014
  • Re: How to make FPGA symbol for schematic
    The only time I manually type in pin names is on something with fewer than 6 pins.  Check out the EDABuilder app from EMA-EDA. Zero retyping... From either the Altera BSM file or a spreadsheet. Extracted the pinmap for Intel's 2011-pin Pentium package recently from their datasheet PDF. And, their footprint builder rocks too.   ...
    Posted to PCB Design (Forum) by Robert Finley on Thu, Mar 6 2014
  • Re: How to change the center drill point (black dots)as some other symbol in allegro??
    You're looking at the drill-size check plot of your drill data.  You're getting that, so it looks like you're generating the drill information correctly.You need to add an artwork film that draws the manufacturing drill legend and drill symbol layers, plus the board outline.  It's traditional to add overall board ...
    Posted to PCB Design (Forum) by Robert Finley on Mon, Feb 24 2014
  • Re: [Help] PADS layout to Allegro PCB translation
    Only thing we noticed is the translated symbols left us without DFA or placement DRC boundaries. The translator makes no attempt to reuse existing padstacks.  Just builds new padstacks with a serial number each time.Used our library automation to generate a second library with footprint names matching what we had in PADS (we didn't ...
    Posted to PCB Design (Forum) by Robert Finley on Sat, Jan 4 2014
  • Re: Attaching Different Nets
    I have to think fabricators are calling with questions (and putting the job on hold) when shorted nets aren't specified in the fab drawing notes. If you design power systems with force/sense lines, it is faster/safer to check the sense location if the short is a physical component.  ATE testing of a 120-pin PMIC device with 16-30 ...
    Posted to PCB Design (Forum) by Robert Finley on Sat, Dec 28 2013
  • Re: How to Pass Shorted Nets from Schematic to PCB Board
    We use a large number of deliberate short "components" on the schematic, typically smaller than 0402 packages.  Beats scraping soldermask off of a trace for changing interrupt assignments.  For sense lines, easier to check the design if it's a separate net. 8-mil pads and an 8-mil line without soldermask should be ...
    Posted to PCB Design (Forum) by Robert Finley on Sat, Dec 28 2013
  • Re: [Need Help]Cadence16.6 Entry point not found, could not be located in the dynamic link library ordb_dll.dll
    Your system seems to fall over before the license is read. Welcome to DLL-hell.  You avoided the 1024 Sys path variable limit by moving CDSROOT near the beginning. Are you using [Windows Start] [Cadence] [Release 16.6] [Allegro] ? If you copy shortcuts to the Task bar, start Menu, and desktop from that menu, they are version ...
    Posted to PCB Design (Forum) by Robert Finley on Sat, Dec 28 2013
  • Re: typical Allegro learning curve ?
    Engineers are responsible for expensive proto builds working when they come back (no amount of money will make up for lost time). Each time I work with a PADS shop, we have this reocurring theme about missed schedules, crushing NRE/labor costs, and turning away business opportunities.  PADS is a cheap "just connect the dots" ...
    Posted to PCB Design (Forum) by Robert Finley on Fri, Dec 20 2013
  • Re: How to connect vias to specific layers
    I've seen the requirement of a signal via (50 ohms) with ground vias adjacent to it.  Ground via spacing was critical to the impedance.    As a bonus, ground vias could only be connected to planes adjacent to the signal layer (ATE fixture.) Would be a lot easier if we could add voids to the padstack.  In the meantime, vias ...
    Posted to PCB Design (Forum) by Robert Finley on Fri, Dec 13 2013
Page 1 of 7 (70 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »