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 Community Search 

Page 1 of 1 (7 items)
  • Re: Dynamic Shape not filled in APD16.6
    Look at the local shape parameter settings.  If you want to "merge" the same-net shape with the pad, set the Thermal relief connect for SMD pins to "Full Contact".  If different nets are in close proximity to the shape, you may need to adjust the shape suppression setting, under the Void controls tab in the shape ...
    Posted to IC Packaging and SiP Design (Forum) by mikem on Wed, Jan 15 2014
  • Re: Warning message in Cadence SiP Layout XL when importing netlist
    Just a guess, but it would seem like when the design was originally created, these function properties were assigned to symbols through logic that was imported from Concept HDL, or another schematic capture program.  Then, instead of importing logic again by the same method (Concept HDL), you simply imported the logic thru a standard netlist ...
    Posted to IC Packaging and SiP Design (Forum) by mikem on Mon, Dec 6 2010
  • Re: SIP16.3 / How to modify netname
    First you will need to set the Cadence tool, so that net renaming is enabled (the default setting is off).  Go into SETUP>USER PREFERENCES in your tool bar.  Scroll down to LOGIC in the pop-up window.  Check the value for the preference: “logic_edit_enabled”.  Select APPLY and OK.   To rename a net, ...
    Posted to IC Packaging and SiP Design (Forum) by mikem on Tue, Jul 27 2010
  • Re: Shape option in Via Structure
    The shape would have to be encorporated into a padstack.  For example, define a via pad that uses a shape for the pad geometry.  Incorporate this this via, with integral shape, into a new via structure.
    Posted to IC Packaging and SiP Design (Forum) by mikem on Tue, Jun 8 2010
  • Re: Importing vias in Allegro APD
    This can be done by using a script: 1.  Open the text file that contains your via coordinates.  Insert the word "pick" and a space, before each coordinate.  Example: pick 2.350 4.560. This may be easiest to do, in Microsoft Excel. 2.  In your design, Place via_150, in an unused area. 3.  ...
    Posted to IC Packaging and SiP Design (Forum) by mikem on Tue, Jun 8 2010
  • Re: How to void shape for same net Bond Finger in APD16.2
    One way is to enter in the desired, same net spacing value in Constraint Manager.  Next, go the the command menu and select EDIT>PROPERTIES and select the same net bondfinger/s.  In the Available Properties pop-up window, select "No_Shape_Connect".  The dynamic shape should immediately void around the ...
    Posted to IC Packaging and SiP Design (Forum) by mikem on Tue, Jun 8 2010
  • Re: same net, 2 constraint values
    It seems Cadence looks at the entire cline (vs.cline segments), when applying spacing constraints within a region.  This isn't good, but it's what you have to work with. Off hand, a quick work around would be to terminate the cline, where the cline width changes inside the constraint region.  For example, route the trace at the ...
    Posted to IC Packaging and SiP Design (Forum) by mikem on Thu, Oct 22 2009
Page 1 of 1 (7 items)