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 Community Search 

Page 1 of 2 (12 items) 1 | 2 | Next >
  • Can spef file from extractRC contain the pin capacitances?
    Hi, I have to process the from encounter generated spef file. In there is everything I need, with one exception. For an input pin, the spef file does not state the pins capacitance with "*L capValue" but insteadt it given a driver with "*D cellName", which it should do only for output pins.Is there any option to include the ...
    Posted to Digital Implementation (Forum) by schnufff on Mon, Jun 30 2014
  • Re: Nanoroute stops at Placement blockage
     Hi Kari, after reading the manual, I am able to route the wires manually without problems. I also can see the pins of the IOs at layer M2 and M3. There is no attribute like special/power/whatever set to the wires.  The lef files of the cells have CLASS PAD INOUT, the Pins have USE SIGNAL, and a PORT definition with the metal layers. ...
    Posted to Digital Implementation (Forum) by schnufff on Wed, Apr 24 2013
  • Re: Nanoroute stops at Placement blockage
    Dear Kari, I figured out, that is has nothing to do with the placement blockage. Beside the  "fully connected" attribute it seems to be related to these to errors: #WARNING (NRDB-733) and #WARNING (NRDB-629) A cadence solution points to a failure in the lef ...
    Posted to Digital Implementation (Forum) by schnufff on Tue, Apr 23 2013
  • Re: Nanoroute stops at Placement blockage
     I think it has to do with the following error: NET  $net is marked as fully connected but pin $pin of instance  $instance is not yet connected. This is repeated for all toplevel nets going to the IO cells. How can I reset these nets, so that they will be routed again?   Stefan
    Posted to Digital Implementation (Forum) by schnufff on Thu, Apr 18 2013
  • Nanoroute stops at Placement blockage
    In my design with 5 cores I have a Placement blockage around each core. This was suggested by Kari to stop sroute from connecting all follow pins together. But now CTS and also nanoroute stops routing all signal that run from the cores trough the blockage to the IO pads. I though its a placement blockage and not a routing blockage. Trial route ...
    Posted to Digital Implementation (Forum) by schnufff on Thu, Apr 18 2013
  • Re: Power domains or not?
     Hi Kari,   sorry for the late reply. I was busy with paperwork. I managed to connect the global nets correctly and also constrainted the follow pins as you suggested. Now the next problem: When I add TieHiLow cells or do CTS, how can I control to which vcc_core_x (x in 1 to 5) the by Encounter added cells will be connected. All ...
    Posted to Digital Implementation (Forum) by schnufff on Mon, Apr 8 2013
  • Re: Power domains or not?
     Hi Kari, thanks for the reply To make it clearer: We are only powering one core via external vcc at a time. There is no need for power switches. The used lib even does not have and power awareness. My problem in the moment is, that the power supply lines of the standard cell rows are always connected to the last used ...
    Posted to Digital Implementation (Forum) by schnufff on Thu, Jan 10 2013
  • Power domains or not?
    Hi all, I have to setup a chip with 5 completely separated cores. Each core has its own vcc_core/io and vdd_core/io ind i/o pins. But the actual voltage of all cores is 1.8V. For testing only one core should be active at a time. Can I do this just with connectGlobalNet or is this more like a multi supply voltage flow with a single ...
    Posted to Digital Implementation (Forum) by schnufff on Thu, Jan 10 2013
  • Re: Howto add more than one Tie High Cell
    Thank you Brian, exactly what I was looking for.   Cheers Stefan  
    Posted to Digital Implementation (Forum) by schnufff on Mon, Mar 19 2012
  • Howto add more than one Tie High Cell
     Hi, in my design, the IO cells have configurable output strength, slew rate and so on. So I hardwired the configpins to something like b'0110. Because my std cell lib contains tie high/low cells I used the addTieHiLo command to add them. But encounter added only one cell in the center of my design. Therefore I have one very long wire to ...
    Posted to Digital Implementation (Forum) by schnufff on Mon, Mar 19 2012
Page 1 of 2 (12 items) 1 | 2 | Next >