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 Community Search 

Page 1 of 1 (3 items)
  • EPS - Dynamic Power Analysis using Vectorless approach
    What is the recommended flow for this? If we have an SDC file, which components of the SDC file affect the power analysis result?  Such as the clock period & the capacitive load on the primary outputs have obvioius ramnifications?  How do false paths affect the result?  Questions such as these.
    Posted to Digital Implementation (Forum) by sobaesq on Tue, Jun 12 2012
  • check_power_library - coupling capacitances.
    How is the coupling capacitances in the reports generated by check_power_library calculated?  I am trying to do a quick-and-dirty calculation to verify if the value is "accurate" .  In addition, are the number of taps a direct relationship to the number of labels?  This exercise is on standard cells.
    Posted to Digital Implementation (Forum) by sobaesq on Mon, Apr 23 2012
  • Re: boundary scan chain clock routing
    Is your scenario where the "clock" buffer is being placed in the middle of the design (floorplan) and fanning out to the respective IO boundary scan cells/modules?   Are you using Cadence RC-DFT to insert boundary scan?  Is it only the clock signal causing you problems?
    Posted to Digital Implementation (Forum) by sobaesq on Mon, Nov 16 2009
Page 1 of 1 (3 items)