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Page 1 of 1 (3 items)
  • Schematic lost on Allegro Design Entry CIS
    Hi, I've been using allegro design entry cis on a project and so far it was working fine. Today, when I opened the project, I realized there was no schematic on it, only the design cache and the Outputs (since I already created the netlist for PCB Planner).  On the session log, there is the following error:  INFO(ORDBDLL-1187): ...
    Posted to PCB Design (Forum) by Joao Demier on Fri, Jul 19 2013
  • Re: Doubts about Allegro Design Entry HDL
    Thank you all very much for your help. For what I understand from your quotes, HDL is more suitable for a corporate environment because one administrator sets all the libraries and configurations while the users only use them. This is actually something desirable on our current situation. I'll search for tutorials to learn how to set up ...
    Posted to PCB Design (Forum) by Joao Demier on Wed, Jun 26 2013
  • Doubts about Allegro Design Entry HDL
    Hi,  I've been using the Allegro Design Entry Cis for quite some time but now the company decided to start using the Design Entry HDL, so we could take the advantage of using constraint manager rules directly on the schematic. I already found out how to convert capture libraries using the Librarian Expert, but I still have some doubts ...
    Posted to PCB Design (Forum) by Joao Demier on Tue, Jun 25 2013
Page 1 of 1 (3 items)