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 Community Search 

Page 1 of 1 (2 items)
  • testflow phases
    Hi all ,          I have some issues in running the test flow phases and i am getting some unpredicted behaviour ,please provide me with some debugging construct in testflow as i am unaware how to use it please provide me with some example.   thanks and regards, selv
    Posted to Functional Verification (Forum) by specmane on Thu, Feb 25 2010
  • canit able to connect the ports
    Hi all, I have an OVC OVC_A which has a sigmap signal sig_p : list of bit. i need to use this OVC to create other OVC OVC_B which has three diffrent signal consider sig_a ,sig_b ,sig_c.  In OVC_A the signal is binded as external. so i extended the sigmap and made as empty. and i tried to connect the OVC_A sig_p with OVC_B sig_a ,sig_b and ...
    Posted to Functional Verification (Forum) by specmane on Fri, Feb 12 2010
Page 1 of 1 (2 items)