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 Community Search 

Page 1 of 2 (14 items) 1 | 2 | Next >
  • Reg Leakage Power in Cadence Encounter
    Hello,  Does any one know how to find leakage power in Cadence encounter ? Does any one know what is the command for leakage power in Cadence Encounter. Please help me... Thanks,  
    Posted to Digital Implementation (Forum) by Music on Sat, Feb 27 2010
  • REG CADENCE Encounter 90nm/65nm library Files
    Hello,    I would like to know some info. regarding Library files thaat are req for my CADENCE Project at nodes 90nm and 65nm. what are the necessary files that i need to have when i mean 90nm library files for Encounter. My prof like to get them. SO i am eager to knwo what should be the files so that i will not get any errors when i ...
    Posted to Digital Implementation (Forum) by Music on Fri, Feb 26 2010
  • Power Grid Library
    Hi.. I am trying to find the Power Analysis for my design. I need Power Grid Libraries. So please help me in getting them. i would like to know how can i get them or will they be embeded in our regular(lib/lef) Library folders. please help me..... I studided the User Guide but there was no Information.  
    Posted to Digital Implementation (Forum) by Music on Thu, Dec 10 2009
  • Re: Encounter v7.1 warnings and errors
     Save this life as aes.lef and try to use this file as your .lef file for your design.....
    Posted to Digital Implementation (Forum) by Music on Mon, Nov 23 2009
  • Regarding Constraint file generation
    Hi..  How can i generate a constraint file for my design? How is it possible to generate design.constr  if my design has clock in it? how is it possible to generate design.constr if my design doesnt have any clock ?  please help me.....
    Posted to Digital Implementation (Forum) by Music on Sat, Nov 21 2009
  • Reg IO pads
    Hi..   I would liketo know how can i view my IO pads...? In ordder to view them what are the necessary files. How can i obtain them? i use SoC encounter 8.1 so please let me know how can i view thwm and  if possible please give an example....  
    Posted to Digital Implementation (Forum) by Music on Fri, Nov 20 2009
  • Reg Power grid library .cl file generation
    Hi,     I am using cadence encounter 8.1 I would like to know how can i generate .cl file for my power grid librarry. So please help me.. but dnt say to look user giide.. i went through it but i cudnt find any answer.. so please help me....
    Posted to Digital Implementation (Forum) by Music on Mon, Nov 16 2009
  • Re: Reg static and dynamic Power Analysis
     Hi..   Thanks for your reply. I dnt have NCSIM . So is there any more chance for me to generate vcd file with modelsim/xilinx .. And i also need osme help in generating Power grid librarry i.e .cl file. Do you know hoew to generate ./ i saw the user guide but there was nothing regarding .cl file generation ? so if u can help me i will ...
    Posted to Digital Implementation (Forum) by Music on Mon, Nov 16 2009
  • Re: Reg .VCD file generation
    Thanks TAM1, Basically i need to calculate the power analysis in SoC Encounter. So for it i need a vcd file. Basically i have my design.v, design_testbench.v, design.sdf, .lib files, .lef files , design.sdf files that i obtained from rtl compiler. I have Model sim, xilinx and cadence encounter with me. I dnt have NC-Verilog , So i dnt use any ...
    Posted to Logic Design (Forum) by Music on Thu, Nov 12 2009
  • Re: Reg .VCD file generation
     I saw your url and it was different andi couldnt get ehat i need.. i need the whole procedure to generate a vcd file either from rtl compiler or xilinx or modelsim... please help me this issue ir related to my thesis ....
    Posted to Logic Design (Forum) by Music on Thu, Nov 12 2009
Page 1 of 2 (14 items) 1 | 2 | Next >