Home > Community > Search
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

 Community Search 

Page 1 of 8 (77 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »
  • Re: TIE-HI and TIE_LO cells
    TIE-HI and TIE-lo cells are already tied to constant 1-logic and costant 0-logic respectively.   To connect gates that are driven to constant 1 or 0 to tie cells, in RTL compiler there is command   'insert_tiehilo_cells -hi TIEHI_A7TULL -lo TIELO_A7TULL -all -maxfanout 20 -verbose' To have global net connectivity ...
    Posted to Digital Implementation (Forum) by diablo on Wed, Jul 18 2012
  • How to evaluate removal check for asynchronous reset?
    I have removal check violation during timing analysis. When I looked at the report, the asynchronous reset goes to two flops, one is clocked by the clock twice faster than the other one. The two clocks are synchronous(same phase). While calculating removal check for slower clock, it is adding one clock period phase shift. This is making the ...
    Posted to Digital Implementation (Forum) by diablo on Mon, Jun 25 2012
  • How to replace single row via with multiple row? Any dbGet solutions?
    I am trying to find and replace all VIA5 that are single row with double row keeping the column of via same as before. One of those via has 1 row and 9 column, whose name is MT_M5_sym_2. I have to change it to 2 row and 9 column. I was going to try this solution which I found in cadence support. # Specify the via to replace with setViaEdit ...
    Posted to Digital Implementation (Forum) by diablo on Tue, Jun 19 2012
  • Re: How to clear connectivity error on special routes
    The image you have attached looks like complete routing is done instead of just sroute. If you have issue with sroute, check you Macro LEF to see if those power/ground pins that you are trying to sroute are indeed defined as POWER/GROUND. Secondly, you need to verify that GlobalnetConnect has been applied to power/ground pin of your MACRO. For ...
    Posted to Digital Implementation (Forum) by diablo on Sat, Jun 9 2012
  • Re: TIE-HI and TIE_LO cells
    No. VDD/VSS if tied directly to gate of NMOS/PMOS, noise in the power supply may turn on the gate. This effect is mitigated by using special cells like TIEHI and TIELO that prevent the MOS from inadvertently turning on with power/ground bounce.
    Posted to Digital Implementation (Forum) by diablo on Mon, May 7 2012
  • Re: Clock Gating as a generated clock in SDC file
    The other way to constraint clock gating and check that output of the gating cell is not clipped clock, you can use  set_clock_gating_check -setup xx -hold xx [get_clock CLK]  in your SDC.    
    Posted to Digital Implementation (Forum) by diablo on Thu, May 3 2012
  • wreal to logic connect module
    For our mixed signal top level verification, we have wreal models for all our analog blocks ( no electrical). I am trying to run a mixed simulation using irun. Starting INCISIV 11.1, there is an automatic insertion of a connect module between wreal to logic using R2L and L2R connect modules. I am using, irun +dr_info -discipline logic -disres ...
    Posted to Functional Verification (Forum) by diablo on Mon, Feb 13 2012
  • Re: Regarding advance TCL scripts
    There might be alternative to using this tcl script. Take a look at 'report_timing' command reference. You can probably do something like report_timing -from start_point -min_slack 0.0 -view 'your analysis view'
    Posted to Digital Implementation (Forum) by diablo on Fri, Jan 20 2012
  • Re: SDF Errors
    Check in you ncelab/irun log file for:      Annotating SDF timing data:         Compiled SDF file:     Your_Design.sdf.X         Log file:              logs/design.log    ...
    Posted to Digital Implementation (Forum) by diablo on Tue, Jul 26 2011
  • Re: ncelab: segmentation of a signal
    Thanks Scrivner. I have all those globalNetConnect defined and i do run them after floorplan. The problem is with my netlist out of RTL compiler. There were some ports tied to constants and not replaced with tiehi/tielo connection.I am using ' insert_tiehilo_cells -hi TIEHI_A7TULL -lo TIELO_A7TULL', which actually doesn't replace all ...
    Posted to Digital Implementation (Forum) by diablo on Mon, Jul 18 2011
Page 1 of 8 (77 items) 1 | 2 | 3 | 4 | 5 | Next > | Last »