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Tom Anderson

Tom leads marketing for the Universal Verification Methodology (UVM) and the Open Verification Methodology (OVM) at Cadence and manages the product marketing team responsible for all verification software products.

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Some Final Real-World Assertions for the Holidays
My last "real-world assertions" blog post seems to have tickled a bunch of people with my story about the racy narration at the historic Red Fort in Delhi. I've heard from several folks who have also seen the show and had a similar reaction   Read More »
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Embracing Our Competitors with the Connections Program
In my last blog post , I described the Cadence Verification Alliance (VA) and how it provides value to customers, VA members, and us. I've been pleasantly surprised at the readership numbers given that this is what radio commentator Paul Harvey used   Read More »
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Secrets of the (Verification) Alliance
In a recent post , I discussed the need for cross-vendor cooperation in EDA, especially in my world of functional verification. It takes a blend of innovative technologies and methodologies to verify a modern system-on-chip (SoC). Customers also need   Read More »
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India Needs Real-World Assertions Too
I've just returned from a week-long trip to India, spending most of my time at the Cadence R&D center in Noida. I was last there a year ago for our CDNLive! India 2010 event, a great show that prompted me to write a glowing blog post . This year's   Read More »
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Verification and the Need for Collaboration
Earlier this week I was at the ARM TechCon in Santa Clara, a show that gets better and busier every year. I was walking around the expo floor, checking out the new vendors and saying hello to old friends, when I got into a conversation with one of our   Read More »
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Too Many Missing Real-World Assertions?
Well, here I am embarking on my fifth post in which I point out illogical situations I'm come across in my daily life and suggest that the real world is missing some useful assertions. What started out as a fun way to fill a blog post has turned into   Read More »
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Missing Real-World Assertions in Computer-Land
I was reviewing the page view statistics on the Cadence Functional verification blog and noticed that my previous three posts about missing real-world assertions are among the most read. So, in the spirit of milking the cash cow, I've collected a   Read More »
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Rumors of SystemVerilog’s Death Have Been Greatly Exaggerated
Our friend and fellow blogger JL Gray recently published a post with the provocative title "UVM and the Death of SystemVerilog." That sure raised some eyebrows here at Cadence and elsewhere, leading to a flurry of tweets debating several of   Read More »
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Everything New is Old … Everything Old is New
The title of this post is taken from a fairly obscure 1982 record album (yes, vinyl) on which several classic doo-wop groups performed versions of then-current songs. It's achieved a bit of cult status since Joey Ramone contributed a song called "Doreen   Read More »
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What Does SystemC Mean for Design and Verification?
My colleague Jack Erickson recently published in the Cadence System Design and Verification Community a blog post entitled "IP Cannot Be an Efficient Abstraction Level without SystemC!" When I saw the title, my immediate reaction was to write   Read More »
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