DAC 2013 – Cadence Customers, Partners Speak About Design Challenges and Solutions
By
Richard Goering
on
May 21, 2013
If you want to know how Cadence customers and partners are solving design and verification challenges, you can find out at the Cadence Theater at the Design Automation Conference ( DAC 2013 ) in Austin, Texas June 3-5. At last count nearly 50 customer
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Tempus – Parallelized Computation Provides a Breakthrough in Static Timing Analysis
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Richard Goering
on
May 20, 2013
Cadence this week (May 20, 2013) announced the Tempus Timing Signoff Solution , a new static timing analysis and closure tool that offers significant speed and capacity advantages over existing solutions. Tempus promises to accelerate signoff timing closure
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DAC 2013: “IP Talks!” Shows What’s New in Semiconductor IP
By
Richard Goering
on
May 16, 2013
If you're working with semiconductor IP at any phase of the design and verification process, the IP Talks! presentations at the ChipEstimate.com booth at the upcoming Design Automation Conference (DAC 2013) will provide a great deal of useful information
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DAC 2013: User Perspectives on System-Level Verification
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Richard Goering
on
May 15, 2013
The best way to learn about an emerging technology is to hear from the people who are using it. If you're curious about system-level design and verification, you can do just that at the Cadence System-to-Silicon Verification Breakfast at the Design
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A CPF User Perspective on IEEE 1801 (UPF) “Methodology Convergence”
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Richard Goering
on
May 13, 2013
By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer
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Joe Costello at EDAC: “Secrets” for Telling a Compelling Company Story
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Richard Goering
on
May 5, 2013
There is no doubt that Joe Costello, the first Cadence CEO, knows how to tell a compelling company story. Under his charismatic leadership, Cadence experienced explosive growth after its formation in 1988, becoming the largest EDA company within just
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Designer View – How GigaOpt in Encounter Digital Implementation (EDI) System 13.1 Boosts IC Design Quality
By
Richard Goering
on
May 1, 2013
If you want to design faster chips in a shorter period of time, the new GigaOpt preRoute technology in the EDI System 13.1 release may be the solution. A detailed look at the GigaOpt preRoute technology came from a CDNLive Silicon Valley presentation
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EDPS Workshop – a Review of FinFET Parasitic Extraction Challenges
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Richard Goering
on
April 29, 2013
There's a lot of excitement about the use of FinFETs at advanced process nodes, and no wonder, given their potential power and performance advantages over planar transistors. But CAD and methodology challenges remain, particularly when it comes to
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GLOBALFOUNDRIES at CDNLive: Why 10nm Requires Design Technology Co-Optimization
By
Richard Goering
on
April 29, 2013
It's not too early to start thinking about the 10nm process node and beyond - but such advanced process nodes will require a significant change in the semiconductor design ecosystem, according to Jongwook Kye, fellow for lithography modeling and architecture
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Cadence DAC 2013 and Denali Party Update
By
Richard Goering
on
April 25, 2013
A very special Design Automation Conference (DAC) will take place in early June - it's the 50 th anniversary of this conference, which has long been a focal point of the EDA industry. This year Cadence is celebrating its 25 th anniversary and has
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