Q&A: GSA Working Group Tackles Barriers to 3D-IC Adoption
By
Richard Goering
on
May 21, 2012
The Global Semiconductor Alliance ( GSA ) 3D IC Working Group is helping pave the way to mainstream adoption of 3D-ICs. With around 275 members, this group provides a neutral forum in which representatives of EDA vendors, design services houses, foundries
Read More »
Comments
(0)
|
 |
Semico Conference: “System Driven” Semiconductor IP Leads to IP Subsystems
By
Richard Goering
on
May 17, 2012
A "new breed" of semiconductor intellectual property (IP) is required for the next stage of evolution in the IP ecosystem, according to a keynote speech by Vishal Kapoor (right) of Cadence at the Semico Impact Conference May 16, 2012. This new
Read More »
Comments
(0)
|
|
|
How IP Subsystem Will Speed NVM Express (NVMe) Adoption
By
Richard Goering
on
May 15, 2012
Non-Volatile Memory Express (NVM Express or NVMe) is an emerging protocol standard for accessing solid state drives (SSDs) over PCI Express (PCIe) links. It would thus make sense, if you're designing an SoC that has an SSD interface, to cobble together
Read More »
Comments
(0)
|
|
|
In-Circuit Acceleration – A New IC Verification Use Model
By
Richard Goering
on
May 15, 2012
Last year Cadence introduced the System Development Suite , a set of four connected hardware/software co-development platforms. Today (May 15, 2012) Cadence is announcing a new release of the System Development Suite that is highlighted by a new verification
Read More »
Comments
(0)
|
|
|
Free DAC Lunches: Custom/Analog Variability, ARM Low Power Processors in Mixed-Signal Designs
By
Richard Goering
on
May 14, 2012
There is such a thing as a free lunch - if you're at the 49th Design Automation Conference (DAC) in San Francisco June 3-7. Cadence is sponsoring two lunches at which you can learn about two important technology topics - custom/analog variability
Read More »
Comments
(0)
|
|
|
Free DAC Breakfasts: HW/SW Co-Development, 28nm/20nm Challenges
By
Richard Goering
on
May 14, 2012
Don't go into the frenzied activity of the Design Automation Conference (DAC) without a good breakfast! Fortunately, you can get a good breakfast and learn a lot from two events sponsored by Cadence Tuesday, June 5 and Wednesday, June 6 at the 49
Read More »
Comments
(0)
|
|
|
Logic Built-in Self Test (LBIST) is Back – But Not for Manufacturing Test
By
Richard Goering
on
May 10, 2012
Memory providers have long used built-in self test (BIST), a technology that builds self-testing circuitry directly into an IC. Logic BIST (LBIST), which tests the functional logic, has been around for a long time too -- but it did not get much traction
Read More »
Comments
(1)
|
|
|
Cadence and IBM Outline 20nm Custom/Analog EDA Flow Requirements
By
Richard Goering
on
May 9, 2012
No 20nm IC design "solution" is complete without a custom/analog flow that can develop standard cells and analog/mixed-signal IP blocks. That custom/analog flow requires some changes to keep up with 20nm challenges such as double patterning
Read More »
Comments
(0)
|
|
|
Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology
By
Richard Goering
on
May 7, 2012
In a recently archived May 2 webinar , speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm
Read More »
Comments
(0)
|
|
|
Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions
By
Richard Goering
on
May 2, 2012
At a recently archived EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant
Read More »
Comments
(0)
|
|
View older posts
»
|