DFT Challenge: Evaluating The True Cost Of Test
By
Richard Goering
on
November 5, 2009
Remember DFT? “Design For Test” faded into the background in recent years as the industry turned its focus to DFM, but if anything test is an even larger concern than it was 10 or 15 years ago. That’s because test is becoming more difficult
Read More »
Comments
(0)
|
 |
Greatest Moments In EDA Innovation
By
Richard Goering
on
November 3, 2009
Innovation is the lifeblood of the EDA industry, and it is only because of innovation from many sources – including academia and industry – that modern IC design is possible at all. Today at Cadence (Nov. 3, 2009), we are celebrating Cadence
Read More »
Comments
(6)
|
|
|
Users Outline New Approaches To Mixed-Signal Verification
By
Richard Goering
on
November 2, 2009
At the Cadence Mixed-Signal Design Summit , held Oct. 27, I had a hard time finding a seat in a packed auditorium. One reason for the summit’s popularity was its hands-on, practical nature. A series of user presentations showed how designers are
Read More »
Comments
(0)
|
|
|
User Interview: How To Estimate Power Early
By
Richard Goering
on
October 29, 2009
Early power estimation makes it much easier to manage IC power, according to Camille Kokozaki, director of design automation services at Integrated Device Technology ( IDT ). At the recent CDNLive! Silicon Valley , he presented a case study of architectural
Read More »
Comments
(0)
|
|
|
Panelists: 32 nm HKMG Is Ready To Roll
By
Richard Goering
on
October 28, 2009
The 32/28 nm Common Platform high-k metal gate (HKMG) technology is “ready and open for business,” according to the title of a breakfast panel at the ARM Techcon3 conference Oct. 22. Panelists from IBM , ARM and Cadence talked about the benefits
Read More »
Comments
(0)
|
|
|
Panelists Broaden Scope Of Low-Power Discussion
By
Richard Goering
on
October 26, 2009
Most of the discussion about low-power design has centered around the RTL-to-GDSII flow for digital ICs. But the real problem is much broader, according to panelists from AMD , Sonics , Wipro , and Cadence at the recent Power Forward Initiative (PFI)
Read More »
Comments
(0)
|
|
|
User Interview: An Under The Hood Look At PDKs
By
Richard Goering
on
October 22, 2009
Well-made process design kits (PDKs) are critical for successful IC design, and design teams should keep in touch with PDK technology development, according to Kristin Liu, principal CAD engineer at National Semiconductor . In an interview at the recent
Read More »
Comments
(0)
|
|
|
Cadence’s Andreas Kuehlmann To Head IEEE Council On EDA
By
Richard Goering
on
October 21, 2009
With a deep involvement in conferences, publications, educational programs and awards, the IEEE Council on EDA ( CEDA ) is a behind-the-scenes organization that has a large influence on the professional EDA community. Andreas Kuehlmann, Cadence fellow
Read More »
Comments
(0)
|
|
|
OpenAccess – So Much To Celebrate, So Much To Do
By
Richard Goering
on
October 19, 2009
Two distinct messages emerged from the Silicon Integration Initiative (Si2) OpenAccess Conference last week. One is that the OpenAccess database is a great EDA standards success story, perhaps the biggest such story of all. Another is that there’s
Read More »
Comments
(1)
|
|
|
CDNLive! - How To Succeed At Formal Verification
By
Richard Goering
on
October 15, 2009
Four customer presentations at CDNLive! Silicon Valley , held Oct. 5-16, provided some valuable tips for users and prospective users of formal verification tools. The presenters included three users of Cadence Incisive Formal Verifier (IFV) and one user
Read More »
Comments
(0)
|
|
View older posts
»
|