2012 CES: Top 3 Trends Impacting EDA This Year
By
Joseph Hupcey III
on
January 17, 2012
For years now consumer electronics have driven (nay, saved) the EDA industry. Hence, many events at last week's annual Consumer Electronics Show (CES) in Las Vegas can be extrapolated as leading indicators for the EDA business. While I couldn't
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Report on ARM Techcon 2011: Real and Virtual Software Apps, High-Speed Silicon and Lego Hardware
By
Joseph Hupcey III
on
December 13, 2011
The acid test of any conference is how long the information and lessons learned linger in your mind after the keynotes, panels, and demos wrap up. Like last year, the 2011 edition of ARM Techcon is passing the test of time. Below are some of the highlights
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Report on CDNLive! India 2011: Provocative Keynotes, Detailed Papers, and Robots!
By
Joseph Hupcey III
on
November 7, 2011
Recently I had the honor of presenting the functional verification roadmap at CDNLive! India in Bangalore. With the high quality of content and networking, it was easy to see why attendance has increased year-over-year; and why CDNLive India has become
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Amazon’s New Kindles: More Steps Toward the Paperback Computer
By
Joseph Hupcey III
on
September 28, 2011
While I understand that a new Kindle Fire at $199 MRSP is significantly more than a dime novel, I assert that today's launch of the new Amazon tablets takes us one step closer to the "paperback computer" becoming a reality. Here the term
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What I Learned Traveling Across the Silicon Prairie
By
Joseph Hupcey III
on
August 16, 2011
Inspired by Brian Fuller's cross-country "Drive for Innovation" , last week I jumped at an opportunity to head out and visit customers in the heartland of America. Here were the common themes heard during the trip: (1) Discovering Power
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Video: Discussion with EET’s Brian Fuller on EDA, Engineers, and Social Media
By
Joseph Hupcey III
on
July 21, 2011
At DAC I had the honor of being interviewed by EE Times editor Brian Fuller on my experiments with social media to connect to the communities of engineers that use the products and capabilities I help bring to market. Specifically, I shared with Brian
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Video: Distinguished Engineer Mike Stellfox on UVM, the Debug Bottleneck, and System Realization
By
Joseph Hupcey III
on
June 29, 2011
My colleague and Cadence Distinguished Engineer Mike Stellfox leads a group of trailblazers inside Cadence. Specifically, Mike's group is tasked with moving our most promising prototypes and methodological theories out of their incubators and into
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Video: Duolog at DAC 2011 Update – Automating Design and Verification IP Integration
By
Joseph Hupcey III
on
June 26, 2011
One of the key tenants of the EDA360 vision is the need for scalable, correct-by-construction IP creation and integration of design and verification IP. Duolog is in the vanguard of creating automation to address this challenge, and in this video update
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Video: DAC 2011 Update From NextOp CEO Yunshan Zhu
By
Joseph Hupcey III
on
June 23, 2011
At DAC 2011 I had the opportunity to reconnect with Yunshan Zhu, the CEO of NextOp Software. After a quick update on their flagship product (BugScope 3.0), Yunshan shares his observations on how assertion synthesis can complement the Universal Verification
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Photo Essay and Comments on DAC 2011 in San Diego, CA
By
Joseph Hupcey III
on
June 17, 2011
In addition to the annotated image gallery ( click here or on the image), below are some long form comments on particular aspects of this year's Design Automation Conference (DAC). Cloud computing - the title of Richard Goering's report on this
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