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Tom Volden

After spending a few years designing ICs, I joined Cadence in 1996 as an applications engineer and discovered that I enjoyed and was better suited to the EDA side of IC design rather than design itself. I've since spent time in various roles including applications engineer, Core Competency engineer, and product engineer. I enjoy working with customers to optimize their tool usage and translating their requirements into specs for new feature development.

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What’s New in Virtuoso ADE XL in IC616 ISR6?
In a previous post, I explained the release model used for Virtuoso ADE and ViVA and listed some of the new features that were available in Virtuoso ADE XL in 616 ISR3. Here are more new features that are now available in Virtuoso ADE XL in the recently   Read More »
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What's New(-ish) in ADE XL in IC 616 ISR 3?
Development Model for ADE and ViVA Virtuoso Analog Design Environment (ADE) and ViVA follow a development model that allows new content to be added in every third ISR. These content ISRs receive additional usability testing, product validation, and demonstrations   Read More »
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Efficient Design Migration Using Virtuoso Analog Design Environment GXL
Requirements for decreased time to market, reduced silicon area, and minimized power consumption move more designs to advanced process nodes. However, redesign of circuitry is time-consuming, so it is common to migrate existing designs from previous projects   Read More »
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