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Blogger

Keith Felton

Over 10 years at Cadence focused on Marketing IC Packaging and SiP technolgies; prior to Cadence spent 3 years at ViewLogic defining the ISIS solution for high-speed topology driven design for PCBs; before that spent 8 years with Racal-Redac (which became Zuken-Redac) in Product Marketing responsible for the Visula PCB solution

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Brad Griffin Speaks at DesignCon - Give Him a Listen!!
If you were not lucky enough to be atDesignCon this week, and many of us were not! You might be interested in the streaming interviews posted on line. Click here for link. Scroll down the video soundbites in the right hand pane, list to what Brad says   Read More »
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3D IC or TSV: The Next Phase in Functional Density and Miniaturization
It seems that almost every semiconductor company is thinking or talking about 3D-IC stacking to boost functonal density & performance, reduce design size, reduce power consumption and hopefully reduce cost. An excellent summary of the 3D-IC design   Read More »
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TSV, mainstream or niche?
I'm sure many of you will have read the article in Advanced Packaging click_here where the luminaries at Georgia-Tech talk about how TSV can take us to the next level of functional integration and miniaturization. I have heard several companies (foundries   Read More »
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Analog/RF chip designers don't care about the Package?
So I have an observation that I would your thoughts/input on. On several occassions I have heard from our sales and AE force that in general, chip designers (layout or circuit designers) generally do not care about the IC Package their work-of-art will   Read More »
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Breaking down the 'virtual' wall
In the last 3-4 months I have seen, and been involved in, a flurry of discussions around driving design using manufacturing assembly data. Call it "IP" if you want -- its fashionable!! At least two world-leading assembly and test companies   Read More »
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Verifying multi-technology chips-in-a-SiP, fact or fiction?
With everyone talking about System-in-Package (SiP), one challenge that often gets ignored or overlooked is: How do you go about functionally verifying mixed technology (CMOS, GaAs etc) chips that are interconnected at the package substrate level?"   Read More »
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