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Pete Hardee

Joined Cadence in 2010, after 16 years in EDA including time at Synopsys and CoWare. Currently have marketing responsibility for Cadence's low power solution.

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New Incisive Verification App and Papers at DVCon by Marvell and TI
If you're an avid reader of Cadence press releases (and what self-respecting verification engineer isn't?), you will have noticed in our Incisive 13.2 platform announcement back on January 13 th that Incisive Formal technology, with our new Trident   Read More »
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Ultra Low Power Benchmarking: Is Apples-to-Apples Feasible?
I noticed some very interesting news last week, widely reported in the technical press, and you can find the source press release here . In a nutshell, the Embedded Microprocessor Benchmark Consortium (EEMBC) has formed a group to look at benchmarks for   Read More »
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Low-Power Technology Summit Proceedings Now Available
On October 18, 2012 Cadence held a Low-Power Technology Summit at our San Jose, California headquarters. Experts from Cadence and other leading companies presented the latest low-power design methodologies. Well, it took us a while but you can now view   Read More »
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Perspective on Power: 2012 Survey Predicts 2013 as the Year of DVFS
The recent Low-Power Technology Summit held at Cadence headquarters in San Jose gave us a great opportunity to take the pulse of low-power design by surveying the attendees. Some of the data we got was expected, but there were a couple of surprises. First   Read More »
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Packed House Expected for Cadence Low-Power Technology Summit
It looks like it might be standing room only for latecomers to the Low-Power Technology Summit at Cadence headquarters building 10 auditorium this Thursday (18 October). Registration has been very strong. I'm expecting a great day -- we have a full   Read More »
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Low-Power Design Case Studies: 15 CDNLive! Papers So Far This Year
CDNLive! is back with a bang in 2012, with very strong support from the Cadence user community worldwide. We're three-quarters the way through the events at the time of writing -- you can see the whole program on www.cadence.com at the CDNLive! 2012   Read More »
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Mixed Signals from European Low-Power Designers
Early summer is a good time to visit Europe. I was there for the first couple of weeks in July, before most of Europe disappears on vacation. I spent my time mainly with customers in Germany, Ireland and the UK. It's not the weather that makes it   Read More »
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What’s Cool for Low-Power at DAC?
Low-power design promises to be a key theme of the Design Automation Conference once again! At DAC 2012 at San Francisco's Moscone Center next week (June 4-7), if you need to cover design, implementation and verification of this important subject   Read More »
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Low-Power Design? Brian Bailey Gets It
Hats off to Brian Bailey! If you haven't been following his EDA Designline Power Series on eetimes.com you have been missing out. Throughout April, he's been running a pretty comprehensive series of editorials, opinion pieces and contributed articles   Read More »
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Cadence Customers to Showcase Advanced Low-Power Designs at CDNLive!
CDNLive! Silicon Valley, taking place at the DoubleTree Hotel in San Jose, CA next week from March 13-14, 2012, brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification   Read More »
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